Component : VD55G1_register_map
|
Description : |
|
Block : STATUS
|
Address |
Name |
Description |
Reset |
|
0x000 |
Device identification |
0x5335 4731 |
|
|
0x004 |
Device revision |
0x0202 |
|
|
0x006 |
Warning detected by the firmware |
0x0000 |
|
|
0x008 |
ROM code revision |
0x0252 |
|
|
0x00C |
Revision of the UI to use |
0x0249 |
|
|
0x00E |
Optical revision of the device |
0x0000 |
|
|
0x010 |
Error detected by the firmware |
0x0000 |
|
|
0x012 |
Firmware patch in used |
0x0000 |
|
|
0x014 |
Read-Pattern Vtiming revision |
0x0000 0000 |
|
|
0x018 |
Global Reset-Pattern Vtiming revision |
0x0000 |
|
|
0x01A |
Global Transfer-Sequence Vtiming revision |
0x0000 |
|
|
0x01C |
Sensor system FSM status |
0x0001 |
|
|
0x01E |
NVM status |
0x0000 |
|
|
0x028 |
Integer part of the external clock frequency in Hz |
0x0000 0000 |
|
|
0x02C |
PLL output frequency in Hz |
0x0000 0000 |
|
|
0x030 |
Pixel clock frequency in Hz |
0x0000 0000 |
|
|
0x034 |
MCU clock frequency in Hz |
0x0000 0000 |
|
|
0x038 |
PLL multiplier value |
0x00 |
|
|
0x039 |
Error detected in the clock tree |
0x00 |
|
|
0x03A |
Address used for I2C/I3C |
0x0020 |
|
|
0x03C |
Last temperature measured with the thermal sensor |
0x0000 |
|
|
0x03E |
Frame rate |
0x0000 |
|
|
0x040 |
Global frame counter |
0x0000 |
|
|
0x042 |
Context frame counter |
0x0000 |
|
|
0x044 |
Number of frames for the context in use |
0x0000 |
|
|
0x046 |
Current context |
0x00 |
|
|
0x047 |
The next context to be streamed after a RepeatCount number of frames are streamed out |
0x00 |
|
|
0x048 |
Image orientation |
0x0000 |
|
|
0x04A |
Video timing controls |
0x00 |
|
|
0x04B |
Frame output format control |
0x00 |
|
|
0x04C |
Configuration of the output interface |
0x0000 |
|
|
0x04E |
Virtual channel |
0x00 |
|
|
0x04F |
Data type for the image data |
0x00 |
|
|
0x050 |
Data type for ISL |
0x00 |
|
|
0x051 |
PLL status |
0x00 |
|
|
0x052 |
Pattern generator control |
0x0000 |
|
|
0x054 |
Applied coarse integration lines A |
0x0000 |
|
|
0x056 |
Applied analog gain |
0x0000 |
|
|
0x058 |
Digital gain, applied from the exposure algorithm channel 0 |
0x0000 |
|
|
0x060 |
Exposure mode control |
0x00 |
|
|
0x061 |
Status of the auto exposure A |
0x00 |
|
|
0x062 |
Mean energy of the input image for the auto exposure A |
0x0000 |
|
|
0x064 |
Applied line length |
0x0000 |
|
|
0x066 |
Digital gain, computed by the exposure in automatic mode |
0x0000 |
|
|
0x068 |
Applied frame length |
0x0000 0000 |
|
|
0x06C |
Image X start from the video timing |
0x0000 |
|
|
0x06E |
Image X end from the video timing |
0x0000 |
|
|
0x070 |
Image Y start from the video timing |
0x0000 |
|
|
0x072 |
Image Y end from the video timing |
0x0000 |
|
|
0x074 |
Image X size |
0x0000 |
|
|
0x076 |
Image Y size |
0x0000 |
|
|
0x078 |
Streaming readout mode control |
0x0000 |
|
|
0x07A |
Wait time before the next frame, and blanking in lines |
0x0000 |
|
|
0x07C |
Coarse exposure time in lines |
0x0000 |
|
|
0x07E |
Coarse exposure time in lines |
0x0000 |
|
|
0x080 |
Mean energy of the input image |
0x0000 |
|
|
0x082 |
Minimum coarse integration in lines |
0x0000 |
|
|
0x084 |
Maximum coarse integration in lines |
0x0000 |
|
|
0x086 |
Damper output of the CC sigma |
0x0000 |
|
|
0x088 |
Damper output of the SG threshold output |
0x0000 |
|
|
0x08A |
Damper output of the GS noise threshold |
0x0000 |
|
|
0x08C |
Damper output of the mono5 threshold |
0x0000 |
|
|
0x08E |
Damper output of the blend threshold |
0x0000 |
|
|
0x090 |
This register is a marker |
0x00 |
|
|
0x091 |
Input GPIO value if input mode is used |
0x00 |
|
|
0x092 |
Input GPIO value if input mode is used |
0x00 |
|
|
0x093 |
Input GPIO value if input mode is used |
0x00 |
|
|
0x094 |
Input GPIO value if input mode is used |
0x00 |
|
|
0x095 |
Darck calibration configuration |
0x00 |
|
|
0x096 |
Pedestal value used in the DDC block |
0x0000 |
|
|
0x0A8 |
Channel 0 statistics |
0x0000 0000 |
|
|
0x0AC |
Channel 1 statistics |
0x0000 0000 |
|
|
0x0B0 |
Channel 2 statistics |
0x0000 0000 |
|
|
0x0B4 |
Channel 3 statistics |
0x0000 0000 |
|
|
0x0B8 |
Time for start up |
0x0000 0000 |
|
|
0x0BC |
Time for boot |
0x0000 0000 |
|
|
0x0C0 |
Time for PLL update |
0x0000 0000 |
|
|
0x0C4 |
SOF count |
0x0000 0000 |
|
|
0x0C8 |
DarkCal count |
0x0000 0000 |
|
|
0x0CC |
Latch count |
0x0000 0000 |
|
|
0x0D0 |
EOF IT count |
0x0000 0000 |
|
|
0x0D4 |
Latest time for SOF task |
0x0000 0000 |
|
|
0x0D8 |
Latest time for DarkCal task |
0x0000 0000 |
|
|
0x0DC |
Latest time for latch task |
0x0000 0000 |
|
|
0x0E0 |
Latest time for EOF task |
0x0000 0000 |
|
|
0x0E4 |
Latest time for EOF task |
0x0000 0000 |
|
|
0x0E8 |
Coarse exposure time in lines |
0x0000 |
|
|
0x0EA |
Analog gain used |
0x0000 |
|
|
0x0EC |
Digital gain, applied from the exposure algorithm channel 0 |
0x0000 |
|
|
0x0F4 |
Time to run the patch command |
0x0000 0000 |
|
|
0x0F8 |
Counter for IT statistics |
0x0000 0000 |
|
|
0x0FC |
Counter for the ISL general statistics |
0x0000 0000 |
|
|
0x100 |
Counter for IT point |
0x0000 0000 |
|
|
0x104 |
Delay between the integration lines |
0x0000 |
|
|
0x106 |
FSM streaming status |
0x00 |
|
|
0x107 |
Low power mode feasability |
0x00 |
|
|
0x128 |
Coarse exposure time in lines |
0x0000 |
|
|
0x12A |
Coarse exposure time in lines |
0x0000 |
|
|
0x12C |
Auto exposure configuration |
0x00 |
|
|
0x12D |
Auto exposure B status |
0x00 |
|
|
0x12E |
Exposure token status |
0x00 |
|
|
0x12F |
AWU FSM status |
0x00 |
|
|
0x130 |
Mean energy of the accumulator 0 |
0x0000 |
|
|
0x132 |
Mean energy of accumulator 1 |
0x0000 |
|
|
0x134 |
Mean energy of accumulator 2 |
0x0000 |
|
|
0x136 |
Number of dark lines streamed |
0x00 |
|
|
0x137 |
PWL status |
0x00 |
|
|
0x138 |
Number of defects corrected by DEFCOR |
0x0000 0000 |
|
|
0x13C |
ANALOG_READOUT_SETTINGS register |
0x0000 0000 |
|
|
0x140 |
Manufacturer's ID |
0x0104 |
|
|
0x142 |
Noise generator configuration registers |
0x00 |
|
|
0x143 |
True when the reference levels and standard deviations for the current frame can be trusted |
0x00 |
|
|
0x144 |
Status of the auto wake up |
0x0000 0000 |
|
|
0x148 |
Delay between two integrations in VT subtraction mode |
0x0000 0000 |
|
|
0x14C |
Offset for VT-SUB |
0x0000 |
|
|
0x14E |
Mode of the video timing |
0x00 |
|
|
0x14F |
Channel stat IP status |
0x00 |
|
|
0x150 |
Microcontroller tick counts, which is the executed statistics task of the last channel |
0x0000 0000 |
|
|
0x154 |
VT start time |
0x0000 0000 |
|
|
0x158 |
VT stop time |
0x0000 0000 |
|
|
0x15C |
Exposure statistics processing time |
0x0000 0000 |
|
|
0x160 |
Microcontroller tick counts taken by the exposure A compiler |
0x0000 0000 |
|
|
0x164 |
Microcontroller tick counts taken by the exposure B compiler |
0x0000 0000 |
|
|
0x168 |
Frame count when the exposure A compiler runs or starts executing |
0x0000 |
|
|
0x16A |
Frame count when the exposure A compiler finishes executing |
0x0000 |
|
|
0x16C |
Frame count when the exposure B compiler runs or starts executing |
0x0000 |
|
|
0x16E |
Frame count when the exposure B compiler finishes executing |
0x0000 |
|
|
0x170 |
Flag set when pending exposure is absorbed |
0x00 |
|
|
0x171 |
Exposure instance used for the actual frame |
0x00 |
|
|
0x174 |
Coarse exposure integration margin |
0x0000 |
|
|
0x176 |
Nonoverlap exposure limit |
0x0000 |
|
|
0x178 |
Time between frames in LP mode |
0x0000 0000 |
|
|
0x17C |
Task margin left while in LP mode |
0x0000 0000 |
|
|
0x180 |
Longest exposure selected in LP mode |
0x0000 |
|
|
0x182 |
Maximum coarse integration in lines for VT-SUB mode A |
0x0000 |
|
|
0x184 |
Maximum coarse integration in lines for VT-SUB mode B |
0x0000 |
|
|
0x186 |
Maximum coarse integration in lines for VT-multi-exposure mode |
0x0000 |
2
Block : CMD
|
Address |
Name |
Description |
Reset |
|
0x200 |
Register to send command in BOOT state |
0x00 |
|
|
0x201 |
Register to send command in STBY state |
0x00 |
|
|
0x202 |
Register to send command in STREAMING state |
0x00 |
2
Block : SENSOR_SETTINGS
|
Address |
Name |
Description |
Reset |
|
0x220 |
External clock frequency in Hz |
0x00B7 1B00 |
|
|
0x224 |
PLL MIPI clock frequency in Hz |
0x4786 8C00 |
|
|
0x228 |
NVM controls |
0x00 |
|
|
0x229 |
Number of 32-bit words to read/write in burst mode |
0x00 |
|
|
0x22A |
Start address in NVM for read/write burst operation |
0x0000 |
|
|
0x230 |
I2C and I3C controls |
0x0120 |
2
Block : STREAM_STATICS
|
Address |
Name |
Description |
Reset |
|
0x300 |
Line length configuration |
0x0468 |
|
|
0x302 |
Image orientation mode control |
0x0000 |
|
|
0x304 |
Patgen configuration |
0x0000 0220 |
|
|
0x308 |
Force the exposure to start from for the auto exposure |
0x00 |
|
|
0x309 |
ADC modes & Synchronization modes |
0x00 |
|
|
0x30A |
Select frame output format between RAW8 and RAW10 |
0x000A |
|
|
0x30C |
Control of CSI polarity inversion for data lane and clock lane |
0x0000 |
|
|
0x30E |
Virtual channel selection |
0x00 |
|
|
0x30F |
CSI data type selection for RAW Image format |
0x2B |
|
|
0x310 |
CSI data type selection for status lines |
0x12 |
|
|
0x311 |
Enable/disable Ultra-Low Power Mode |
0x00 |
|
|
0x312 |
Auto exposure use case |
0x00 |
|
|
0x313 |
Auto exposure priority |
0x00 |
|
|
0x314 |
Enable logarithm log |
0x01 |
|
|
0x315 |
Minimum difference exposure when using double exposure mechanism |
0x05 |
|
|
0x316 |
Minimum analog gain |
0x00 |
|
|
0x317 |
Maximum analog gain |
0x1C |
|
|
0x318 |
Minimum digital gain |
0x0100 |
|
|
0x31A |
Maximum digital gain |
0x1FFF |
|
|
0x31C |
HDR ratio when in HDr auto exposure mode |
0x0008 0008 |
|
|
0x324 |
I3C readout configuration |
0x0002 |
|
|
0x326 |
Control of the ISL output |
0x01 |
|
|
0x327 |
Padding of the ISL to the image array |
0x01 |
|
|
0x328 |
Delay of the start integration when in slave mode |
0x0000 |
|
|
0x32A |
Control of the dark calibration |
0x41 |
|
|
0x32B |
Control of the PWL |
0x00 |
|
|
0x32C |
Abscissa 0 |
0x0000 |
|
|
0x32E |
Abscissa 1 |
0x0000 |
|
|
0x330 |
Abscissa 2 |
0x0000 |
|
|
0x332 |
Abscissa 3 |
0x0000 |
|
|
0x334 |
Ordinate 0 |
0x0000 |
|
|
0x336 |
Ordinate 1 |
0x0000 |
|
|
0x338 |
Ordinate 2 |
0x0000 |
|
|
0x33A |
Ordinate 3 |
0x0000 |
|
|
0x33C |
Gradient 0 |
0x0000 0000 |
|
|
0x340 |
Gradient 1 |
0x0000 0000 |
|
|
0x344 |
Gradient 2 |
0x0000 0000 |
|
|
0x348 |
Gradient 3 |
0x0000 0000 |
|
|
0x34C |
Abscissa 0 |
0x0000 |
|
|
0x34E |
Abscissa 1 |
0x0000 |
|
|
0x350 |
Abscissa 2 |
0x0000 |
|
|
0x352 |
Abscissa 3 |
0x0000 |
|
|
0x354 |
Ordinate 0 |
0x0000 |
|
|
0x356 |
Ordinate 1 |
0x0000 |
|
|
0x358 |
Ordinate 2 |
0x0000 |
|
|
0x35A |
Ordinate 3 |
0x0000 |
|
|
0x35C |
Gradient 0 |
0x0000 0000 |
|
|
0x360 |
Gradient 1 |
0x0000 0000 |
|
|
0x364 |
Gradient 2 |
0x0000 0000 |
|
|
0x368 |
Gradient 3 |
0x0000 0000 |
|
|
0x36C |
Auto wake up controls |
0x0316 0942 |
|
|
0x370 |
Auto wake up detection threshold |
0x0600 |
|
|
0x372 |
Maximum integration tim |
0x7FFF |
|
|
0x374 |
Cold start for the auto exposure instance A |
0x0000 07D0 |
|
|
0x378 |
Cold start for the auto exposure instance B |
0x0000 07D0 |
|
|
0x37C |
Margin of the integration time compare to the frame length |
0x0039 0039 |
|
|
0x380 |
Minimum integration time |
0x0004 0005 |
|
|
0x384 |
Auto wake up controls |
0x0007 |
|
|
0x386 |
Allowed excess exposure in flicker free in EV for A |
0x0000 |
|
|
0x388 |
Allowed excess exposure in flicker free in EV for B |
0x0000 |
|
|
0x38A |
Compilation problem threshold ration |
0x0133 |
|
|
0x3AC |
Noise generator configuration |
0x007F |
|
|
0x3AE |
Defect correction and noise reduction controls |
0x0013 |
|
|
0x3DC |
Number of frame to be output from context 0 |
0x0000 |
|
|
0x3DE |
Number of frame to be output from context 1 |
0x0000 |
|
|
0x3E0 |
Number of frame to be output from context 2 |
0x0000 |
|
|
0x3E2 |
Number of frame to be output from context 3 |
0x0000 |
|
|
0x3E4 |
Context chaining |
0x1111 |
|
|
0x3E6 |
Offset for the subtraction |
0x0200 |
|
|
0x3E8 |
Delay between 2 frames in subtraction mode |
0x0000 0000 |
2
Block : STREAM_DYNAMICS
|
Address |
Name |
Description |
Reset |
|
0x481 |
Hold the application of the dynamic parameters |
0x00 |
|
|
0x482 |
Controls of the auto exposure A |
0x0000 |
|
|
0x484 |
Exposure compensation for the auto exposure A |
0x0000 |
|
|
0x486 |
Target of the auto exposure A |
0x1B |
|
|
0x488 |
Maximum step of the auto exposure A |
0x0080 |
|
|
0x48A |
Leak proportion of the auto exposure A |
0x1F40 |
|
|
0x48C |
Controls of the auto exposure B |
0x0000 |
|
|
0x48E |
Exposure compensation for the auto exposure B |
0x0000 |
|
|
0x490 |
Target of the auto exposure B |
0x1B |
|
|
0x492 |
Maximum step of the auto exposure B |
0x0080 |
|
|
0x494 |
Leak proportion of the auto exposure B |
0x1F40 |
|
|
0x49C |
Minimum exposure step to change exposure |
0x0002 |
|
|
0x49E |
Maximum exposure step |
0x0400 |
|
|
0x4A0 |
Tolerance of the auto exposure when aligned to the flicker frequency |
0x0500 |
2
Block : STREAM_CTX0
|
Address |
Name |
Description |
Reset |
|
0x500 |
Exposure mode control |
0x02 |
|
|
0x501 |
Manual analog gain |
0x00 |
|
|
0x502 |
Manual coarse exposure |
0x0032 |
|
|
0x504 |
Manual digital gain |
0x0100 |
|
|
0x50C |
Length of the frame |
0x0000 0316 |
|
|
0x510 |
Y start for image output |
0x0000 |
|
|
0x512 |
Y height for image output |
0x02C0 |
|
|
0x514 |
X start for image output |
0x0000 |
|
|
0x516 |
X wIdth for image output |
0x0324 |
|
|
0x518 |
Active zones for the auto exposure statistique computation |
0xFFFF |
|
|
0x51A |
Statistics zone weight |
0x64 |
|
|
0x51B |
Marker used by host |
0x00 |
|
|
0x51D |
Control of the GPIO 0 |
0x01 |
|
|
0x51E |
Control of the GPIO 1 |
0x02 |
|
|
0x51F |
Control of the GPIO 2 |
0x06 |
|
|
0x520 |
Control of the GPIO 3 |
0x02 |
|
|
0x521 |
Capabilty to shift the start of the VSYNC |
0x00 |
|
|
0x522 |
Capabilty to shift the end of the VSYNC |
0x00 |
|
|
0x523 |
Capabilty to shift the start of the STROBE |
0x00 |
|
|
0x524 |
Capabilty to shift the end of the STROBE |
0x00 |
|
|
0x526 |
Pedestal to be applied |
0x0008 |
|
|
0x528 |
Controls of the PWM |
0x0064 0007 |
|
|
0x52C |
Control of the PWL |
0x00 |
|
|
0x52D |
Instance of exposure to be used in this context |
0x00 |
|
|
0x52E |
Decimation control |
0x00 |
|
|
0x530 |
Manual exposure for the second exposure |
0x0032 |
|
|
0x532 |
Manual exposure for the third exposure |
0x0032 |
|
|
0x536 |
Subtraction control |
0x00 |
|
|
0x537 |
Control to mask frames |
0x00 |
2
Block : STREAM_CTX1
|
Address |
Name |
Description |
Reset |
|
0x550 |
Exposure mode control |
0x02 |
|
|
0x551 |
Manual analog gain |
0x00 |
|
|
0x552 |
Manual coarse exposure |
0x0032 |
|
|
0x554 |
Manual digital gain |
0x0100 |
|
|
0x55C |
Length of the frame |
0x0000 0316 |
|
|
0x560 |
Y start for image output |
0x0000 |
|
|
0x562 |
Y height for image output |
0x02C0 |
|
|
0x564 |
X start for image output |
0x0000 |
|
|
0x566 |
X wIdth for image output |
0x0324 |
|
|
0x568 |
Active zones for the auto exposure statistique computation |
0xFFFF |
|
|
0x56A |
Statistics zone weight |
0x64 |
|
|
0x56B |
Marker used by host |
0x00 |
|
|
0x56D |
Control of the GPIO 0 |
0x01 |
|
|
0x56E |
Control of the GPIO 1 |
0x02 |
|
|
0x56F |
Control of the GPIO 2 |
0x06 |
|
|
0x570 |
Control of the GPIO 3 |
0x02 |
|
|
0x571 |
Capabilty to shift the start of the VSYNC |
0x00 |
|
|
0x572 |
Capabilty to shift the end of the VSYNC |
0x00 |
|
|
0x573 |
Capabilty to shift the start of the STROBE |
0x00 |
|
|
0x574 |
Capabilty to shift the end of the STROBE |
0x00 |
|
|
0x576 |
Pedestal to be applied |
0x0008 |
|
|
0x578 |
Controls of the PWM |
0x0064 0007 |
|
|
0x57C |
Control of the PWL |
0x00 |
|
|
0x57D |
Instance of exposure to be used in this context |
0x00 |
|
|
0x57E |
Decimation control |
0x00 |
|
|
0x580 |
Manual exposure for the second exposure |
0x0032 |
|
|
0x582 |
Manual exposure for the third exposure |
0x0032 |
|
|
0x586 |
Subtraction control |
0x00 |
|
|
0x587 |
Control to mask frames |
0x00 |
2
Block : STREAM_CTX2
|
Address |
Name |
Description |
Reset |
|
0x5A0 |
Exposure mode control |
0x02 |
|
|
0x5A1 |
Manual analog gain |
0x00 |
|
|
0x5A2 |
Manual coarse exposure |
0x0032 |
|
|
0x5A4 |
Manual digital gain |
0x0100 |
|
|
0x5AC |
Length of the frame |
0x0000 0316 |
|
|
0x5B0 |
Y start for image output |
0x0000 |
|
|
0x5B2 |
Y height for image output |
0x02C0 |
|
|
0x5B4 |
X start for image output |
0x0000 |
|
|
0x5B6 |
X wIdth for image output |
0x0324 |
|
|
0x5B8 |
Active zones for the auto exposure statistique computation |
0xFFFF |
|
|
0x5BA |
Statistics zone weight |
0x64 |
|
|
0x5BB |
Marker used by host |
0x00 |
|
|
0x5BD |
Control of the GPIO 0 |
0x01 |
|
|
0x5BE |
Control of the GPIO 1 |
0x02 |
|
|
0x5BF |
Control of the GPIO 2 |
0x06 |
|
|
0x5C0 |
Control of the GPIO 3 |
0x02 |
|
|
0x5C1 |
Capabilty to shift the start of the VSYNC |
0x00 |
|
|
0x5C2 |
Capabilty to shift the end of the VSYNC |
0x00 |
|
|
0x5C3 |
Capabilty to shift the start of the STROBE |
0x00 |
|
|
0x5C4 |
Capabilty to shift the end of the STROBE |
0x00 |
|
|
0x5C6 |
Pedestal to be applied |
0x0008 |
|
|
0x5C8 |
Controls of the PWM |
0x0064 0007 |
|
|
0x5CC |
Control of the PWL |
0x00 |
|
|
0x5CD |
Instance of exposure to be used in this context |
0x00 |
|
|
0x5CE |
Decimation control |
0x00 |
|
|
0x5D0 |
Manual exposure for the second exposure |
0x0032 |
|
|
0x5D2 |
Manual exposure for the third exposure |
0x0032 |
|
|
0x5D6 |
Subtraction control |
0x00 |
|
|
0x5D7 |
Control to mask frames |
0x00 |
2
Block : STREAM_CTX3
|
Address |
Name |
Description |
Reset |
|
0x5F0 |
Exposure mode control |
0x02 |
|
|
0x5F1 |
Manual analog gain |
0x00 |
|
|
0x5F2 |
Manual coarse exposure |
0x0032 |
|
|
0x5F4 |
Manual digital gain |
0x0100 |
|
|
0x5FC |
Length of the frame |
0x0000 0316 |
|
|
0x600 |
Y start for image output |
0x0000 |
|
|
0x602 |
Y height for image output |
0x02C0 |
|
|
0x604 |
X start for image output |
0x0000 |
|
|
0x606 |
X wIdth for image output |
0x0324 |
|
|
0x608 |
Active zones for the auto exposure statistique computation |
0xFFFF |
|
|
0x60A |
Statistics zone weight |
0x64 |
|
|
0x60B |
Marker used by host |
0x00 |
|
|
0x60D |
Control of the GPIO 0 |
0x01 |
|
|
0x60E |
Control of the GPIO 1 |
0x02 |
|
|
0x60F |
Control of the GPIO 2 |
0x06 |
|
|
0x610 |
Control of the GPIO 3 |
0x02 |
|
|
0x611 |
Capabilty to shift the start of the VSYNC |
0x00 |
|
|
0x612 |
Capabilty to shift the end of the VSYNC |
0x00 |
|
|
0x613 |
Capabilty to shift the start of the STROBE |
0x00 |
|
|
0x614 |
Capabilty to shift the end of the STROBE |
0x00 |
|
|
0x616 |
Pedestal to be applied |
0x0008 |
|
|
0x618 |
Controls of the PWM |
0x0064 0007 |
|
|
0x61C |
Control of the PWL |
0x00 |
|
|
0x61D |
Instance of exposure to be used in this context |
0x00 |
|
|
0x61E |
Decimation control |
0x00 |
|
|
0x620 |
Manual exposure for the second exposure |
0x0032 |
|
|
0x622 |
Manual exposure for the third exposure |
0x0032 |
|
|
0x626 |
Subtraction control |
0x00 |
|
|
0x627 |
Control to mask frames |
0x00 |
2
Block : NVM_MIRROR
|
Address |
Name |
Description |
Reset |
|
0x648 |
ENG1 register |
0x0000 0000 |
|
|
0x64C |
ENG2 register |
0x0000 0000 |
|
|
0x69C |
I3C register |
0x0000 0000 |
|
|
0x6B8 |
I2C_ADDRESS register |
0x0000 0000 |
|
|
0x6BC |
CTM_AREA_n register |
0x0000 0000 |
|
|
0x73C |
LAST_WORD register |
0x0000 0000 |
2
Block: STATUS
|
Description |
: Status of the firmware and it's functional States |
3
|
Description |
: Device identification |
|
Offset |
: 0x0 |
|
Absolute Address |
: 0x000 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x5335 4731 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x5335 4731 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
VD55G1 device name |
RO - - |
0x5335 4731 |
6
|
Description |
: Device revision |
|
Offset |
: 0x4 |
|
Absolute Address |
: 0x004 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
TOP_DIE |
BOTTOM_DIE |
||||||||||||||
|
RO - 0x02 |
RO - 0x02 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
TOP_DIE |
Top die mask code (HW) |
RO - - |
0x02 |
|
7:0 |
BOTTOM_DIE |
Bottom die mask code (HW) |
RO - - |
0x02 |
6
|
Description |
: Warning detected by the firmware |
|
Offset |
: 0x6 |
|
Absolute Address |
: 0x006 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Warning codes 0x0000 DEFINES_NO_SYSTEM_ERROR: DEFINES_NO_SYSTEM_ERROR 0x0001 DEFINES_SYSTEM_ERROR_ERR0: DEFINES_SYSTEM_ERROR_ERR0 0x0002 DEFINES_MCU_ITC_INIT_IRQ: DEFINES_MCU_ITC_INIT_IRQ 0x0100 CRM_ERROR_PLL_SYS_LOCK_TIMEOUT: CRM_ERROR_PLL_SYS_LOCK_TIMEOUT 0x0101 CRM_ERROR_PLL_DAC_LOCK_TIMEOUT: CRM_ERROR_PLL_DAC_LOCK_TIMEOUT 0x0102 CRM_ERROR_DAC_MULT_DIV: CRM_ERROR_DAC_MULT_DIV 0x0103 CRM_ERROR_DPHY_ESC_RANGE: CRM_ERROR_DPHY_ESC_RANGE 0x0104 CRM_ERROR_THSENS_RANGE: CRM_ERROR_THSENS_RANGE 0x0105 CRM_ERROR_EXT_CLK_RANGE: CRM_ERROR_EXT_CLK_RANGE 0x0106 CRM_ERROR_HOST_CLK_RANGE: CRM_ERROR_HOST_CLK_RANGE 0x0107 CRM_ERROR_PLL_MULT_RANGE: CRM_ERROR_PLL_MULT_RANGE 0x0108 CRM_ERROR_COUNTER_CLK_FREQ: CRM_ERROR_COUNTER_CLK_FREQ 0x0109 CRM_ERROR_PIXEL_CLK_FREQ: CRM_ERROR_PIXEL_CLK_FREQ 0x0200 DEFINES_THSENS_TIMEOUT_ERROR: DEFINES_THSENS_TIMEOUT_ERROR 0x0201 DEFINES_THSENS_DATAREADY_ERROR: DEFINES_THSENS_DATAREADY_ERROR 0x0202 DEFINES_THSENS_TEMP_125_ERROR: DEFINES_THSENS_TEMP_125_ERROR 0x0203 DEFINES_THSENS_TEMP_135_ERROR: DEFINES_THSENS_TEMP_135_ERROR 0x0300 DPHYTX_BASE_ERROR: DPHYTX_BASE_ERROR 0x0400 XP70PATCH_ERROR_PATCH_CODE_TOO_LARGE: XP70PATCH_ERROR_PATCH_CODE_TOO_LARGE 0x0401 XP70PATCH_ERROR_TOO_MANY_PATCHES: XP70PATCH_ERROR_TOO_MANY_PATCHES 0x0402 XP70PATCH_ERROR_TOO_MANY_HOOKS: XP70PATCH_ERROR_TOO_MANY_HOOKS 0x0403 XP70PATCH_ERROR_BAD_CRC: XP70PATCH_ERROR_BAD_CRC 0x0404 XP70PATCH_ERROR_BAD_PATCH_ADDR: XP70PATCH_ERROR_BAD_PATCH_ADDR 0x0405 XP70PATCH_ERROR_BAD_MD5SUM: XP70PATCH_ERROR_BAD_MD5SUM 0x0500 EXCEPTIONS_ERROR_PROTECT: EXCEPTIONS_ERROR_PROTECT 0x0501 EXCEPTIONS_ERROR_OPCODE: EXCEPTIONS_ERROR_OPCODE 0x0502 EXCEPTIONS_ERROR_GPRSIZE: EXCEPTIONS_ERROR_GPRSIZE 0x0503 EXCEPTIONS_ERROR_PMISALIGN: EXCEPTIONS_ERROR_PMISALIGN 0x0504 EXCEPTIONS_ERROR_POUTOFMEM: EXCEPTIONS_ERROR_POUTOFMEM 0x0505 EXCEPTIONS_ERROR_PEXECUTE: EXCEPTIONS_ERROR_PEXECUTE 0x0506 EXCEPTIONS_ERROR_DMISALIGN: EXCEPTIONS_ERROR_DMISALIGN 0x0507 EXCEPTIONS_ERROR_DOUTOFMEM: EXCEPTIONS_ERROR_DOUTOFMEM 0x0508 EXCEPTIONS_ERROR_DREAD: EXCEPTIONS_ERROR_DREAD 0x0509 EXCEPTIONS_ERROR_DWRITE: EXCEPTIONS_ERROR_DWRITE 0x050A EXCEPTIONS_ERROR_PSYSERR: EXCEPTIONS_ERROR_PSYSERR 0x050B EXCEPTIONS_ERROR_OVERFLOW: EXCEPTIONS_ERROR_OVERFLOW 0x050C EXCEPTIONS_ERROR_UNKNOWN: EXCEPTIONS_ERROR_UNKNOWN 0x0600 CRCCCITT_BASE_ERROR: CRCCCITT_BASE_ERROR 0x0700 MULTICROPPER_BASE_ERROR: MULTICROPPER_BASE_ERROR 0x0800 DEFINES_I3C_PAD_COMMS_DRIVE_ERROR: DEFINES_I3C_PAD_COMMS_DRIVE_ERROR 0x0A00 DEFINES_VTIMING_LONG_COARSE_MAX_ERROR: DEFINES_VTIMING_LONG_COARSE_MAX_ERROR 0x0A01 DEFINES_VTIMING_LONG_COARSE_MIN_ERROR: DEFINES_VTIMING_LONG_COARSE_MIN_ERROR 0x0A02 DEFINES_VTIMING_LONG_COARSE_IR_MAX_ERROR: DEFINES_VTIMING_LONG_COARSE_IR_MAX_ERROR 0x0A03 DEFINES_VTIMING_LONG_COARSE_IR_MIN_ERROR: DEFINES_VTIMING_LONG_COARSE_IR_MIN_ERROR 0x0A04 DEFINES_VTIMING_BAD_FRAME_LENGTH_ERROR: DEFINES_VTIMING_BAD_FRAME_LENGTH_ERROR 0x0A05 DEFINES_VTIMING_ISB_LONG_PIPE_OVERFLOW: DEFINES_VTIMING_ISB_LONG_PIPE_OVERFLOW 0x0A06 DEFINES_VTIMING_Y_SIZE_SS_ERROR: DEFINES_VTIMING_Y_SIZE_SS_ERROR 0x0A07 DEFINES_VTIMING_X_SIZE_SS_ERROR: DEFINES_VTIMING_X_SIZE_SS_ERROR 0x0A08 DEFINES_VTIMING_BGISON_LOW: DEFINES_VTIMING_BGISON_LOW 0x0A09 DEFINES_VTIMING_BGISON_HIGH: DEFINES_VTIMING_BGISON_HIGH 0x0A0A DEFINES_VTIMING_TOKEN_NOT_FOUND_ERROR: DEFINES_VTIMING_TOKEN_NOT_FOUND_ERROR 0x0B00 DEFINES_ISP_SDR_FIFO_FULL_ERROR: DEFINES_ISP_SDR_FIFO_FULL_ERROR 0x0B01 DEFINES_ISP_ISLGEN_INVALID_CFG_ERROR: DEFINES_ISP_ISLGEN_INVALID_CFG_ERROR 0x0B02 DEFINES_ISP_ISLGEN_MEMORY_LOCKED_ERROR: DEFINES_ISP_ISLGEN_MEMORY_LOCKED_ERROR 0x0B03 DEFINES_ISP_ISLGEN_MISSED_TRIGGER_ERROR: DEFINES_ISP_ISLGEN_MISSED_TRIGGER_ERROR 0x0B04 DEFINES_ISP_ISLGEN_TOO_MANY_ENTRIES_ERROR: DEFINES_ISP_ISLGEN_TOO_MANY_ENTRIES_ERROR 0x0B05 DEFINES_ISP_MULTICROP_NO_ROI_ERROR: DEFINES_ISP_MULTICROP_NO_ROI_ERROR 0x0B06 DEFINES_ISP_ISB2IDP_LINEBLANKING_ERROR: DEFINES_ISP_ISB2IDP_LINEBLANKING_ERROR 0x0B07 DEFINES_ISP_CHANNELSTATS_CHANNEL_INDEX_ERROR: DEFINES_ISP_CHANNELSTATS_CHANNEL_INDEX_ERROR 0x0B08 DEFINES_ISP_CHANNELSTATS_ROI_ERROR: DEFINES_ISP_CHANNELSTATS_ROI_ERROR 0x0B09 DEFINES_ISP_CHANNELSTATS_STATS_OV_ERROR: DEFINES_ISP_CHANNELSTATS_STATS_OV_ERROR 0x0B0A DEFINES_ISP_PATGEN_ERROR_INVALID_PATTERN: DEFINES_ISP_PATGEN_ERROR_INVALID_PATTERN 0x0B0B DEFINES_ISP_X_Y_ERROR_INVALID_XY_CONFIG: DEFINES_ISP_X_Y_ERROR_INVALID_XY_CONFIG 0x0B0C DEFINES_ISP_CHANNELSTATS_PATTERN_ERROR: DEFINES_ISP_CHANNELSTATS_PATTERN_ERROR 0x0B0D DEFINES_ISP_EXPOSURE_USE_CASE_ERROR: DEFINES_ISP_EXPOSURE_USE_CASE_ERROR 0x0C00 DEFINES_OIF_CSI_LANE_DESYNC_ERROR: DEFINES_OIF_CSI_LANE_DESYNC_ERROR 0x0C01 DEFINES_OIF_CSI_PKT_TOO_LONG_ERROR: DEFINES_OIF_CSI_PKT_TOO_LONG_ERROR 0x0C02 DEFINES_OIF_CSI_PKT_TOO_SHORT_ERROR: DEFINES_OIF_CSI_PKT_TOO_SHORT_ERROR 0x0C03 DEFINES_OIF_CSI_UNDERFLOW_ERROR: DEFINES_OIF_CSI_UNDERFLOW_ERROR 0x0C04 DEFINES_OIF_MERGER_EXT_SYNC_MISSED_ERROR: DEFINES_OIF_MERGER_EXT_SYNC_MISSED_ERROR 0x0C05 DEFINES_OIF_ISB2T1_UNDERFLOW: DEFINES_OIF_ISB2T1_UNDERFLOW 0x0C06 DEFINES_OIF_I3CRDOUT_CONFIG_ERROR: DEFINES_OIF_I3CRDOUT_CONFIG_ERROR 0x0C07 DEFINES_OIF_I3CRDOUT_IBI_ERROR: DEFINES_OIF_I3CRDOUT_IBI_ERROR 0x0D00 DEFINES_GENERIC_BAD_PARAM_NVM_CTRL: DEFINES_GENERIC_BAD_PARAM_NVM_CTRL |
RO - - |
0x0000 |
6
|
Description |
: ROM code revision |
|
Offset |
: 0x8 |
|
Absolute Address |
: 0x008 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
MAJOR_REVISION |
MINOR_REVISION |
MICRO_REVISION |
||||||||||||
|
RO - 0x0 |
RO - 0x2 |
RO - 0x5 |
RO - 0x2 |
||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:12 |
RESERVED0 |
Reserved |
RO - - |
0x0 |
|
11:8 |
MAJOR_REVISION |
Major ROM code revision |
RO - - |
0x2 |
|
7:4 |
MINOR_REVISION |
Minor ROM code revision |
RO - - |
0x5 |
|
3:0 |
MICRO_REVISION |
Micro ROM code revision |
RO - - |
0x2 |
6
|
Description |
: Revision of the UI to use |
|
Offset |
: 0xC |
|
Absolute Address |
: 0x00C |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
MAJOR_REVISION |
MINOR_REVISION |
||||||||||||||
|
RO - 0x02 |
RO - 0x49 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
MAJOR_REVISION |
Major UI revision |
RO - - |
0x02 |
|
7:0 |
MINOR_REVISION |
Minor UI revision |
RO - - |
0x49 |
6
|
Description |
: Optical revision of the device |
|
Offset |
: 0xE |
|
Absolute Address |
: 0x00E |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Optical revision |
RO - - |
0x0000 |
6
|
Description |
: Error detected by the firmware |
|
Offset |
: 0x10 |
|
Absolute Address |
: 0x010 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Error code 0x0000 DEFINES_NO_SYSTEM_ERROR: DEFINES_NO_SYSTEM_ERROR 0x0001 DEFINES_SYSTEM_ERROR_ERR0: DEFINES_SYSTEM_ERROR_ERR0 0x0002 DEFINES_MCU_ITC_INIT_IRQ: DEFINES_MCU_ITC_INIT_IRQ 0x0100 CRM_ERROR_PLL_SYS_LOCK_TIMEOUT: CRM_ERROR_PLL_SYS_LOCK_TIMEOUT 0x0101 CRM_ERROR_PLL_DAC_LOCK_TIMEOUT: CRM_ERROR_PLL_DAC_LOCK_TIMEOUT 0x0102 CRM_ERROR_DAC_MULT_DIV: CRM_ERROR_DAC_MULT_DIV 0x0103 CRM_ERROR_DPHY_ESC_RANGE: CRM_ERROR_DPHY_ESC_RANGE 0x0104 CRM_ERROR_THSENS_RANGE: CRM_ERROR_THSENS_RANGE 0x0105 CRM_ERROR_EXT_CLK_RANGE: CRM_ERROR_EXT_CLK_RANGE 0x0106 CRM_ERROR_HOST_CLK_RANGE: CRM_ERROR_HOST_CLK_RANGE 0x0107 CRM_ERROR_PLL_MULT_RANGE: CRM_ERROR_PLL_MULT_RANGE 0x0108 CRM_ERROR_COUNTER_CLK_FREQ: CRM_ERROR_COUNTER_CLK_FREQ 0x0109 CRM_ERROR_PIXEL_CLK_FREQ: CRM_ERROR_PIXEL_CLK_FREQ 0x0200 DEFINES_THSENS_TIMEOUT_ERROR: DEFINES_THSENS_TIMEOUT_ERROR 0x0201 DEFINES_THSENS_DATAREADY_ERROR: DEFINES_THSENS_DATAREADY_ERROR 0x0202 DEFINES_THSENS_TEMP_125_ERROR: DEFINES_THSENS_TEMP_125_ERROR 0x0203 DEFINES_THSENS_TEMP_135_ERROR: DEFINES_THSENS_TEMP_135_ERROR 0x0300 DPHYTX_BASE_ERROR: DPHYTX_BASE_ERROR 0x0400 XP70PATCH_ERROR_PATCH_CODE_TOO_LARGE: XP70PATCH_ERROR_PATCH_CODE_TOO_LARGE 0x0401 XP70PATCH_ERROR_TOO_MANY_PATCHES: XP70PATCH_ERROR_TOO_MANY_PATCHES 0x0402 XP70PATCH_ERROR_TOO_MANY_HOOKS: XP70PATCH_ERROR_TOO_MANY_HOOKS 0x0403 XP70PATCH_ERROR_BAD_CRC: XP70PATCH_ERROR_BAD_CRC 0x0404 XP70PATCH_ERROR_BAD_PATCH_ADDR: XP70PATCH_ERROR_BAD_PATCH_ADDR 0x0405 XP70PATCH_ERROR_BAD_MD5SUM: XP70PATCH_ERROR_BAD_MD5SUM 0x0500 EXCEPTIONS_ERROR_PROTECT: EXCEPTIONS_ERROR_PROTECT 0x0501 EXCEPTIONS_ERROR_OPCODE: EXCEPTIONS_ERROR_OPCODE 0x0502 EXCEPTIONS_ERROR_GPRSIZE: EXCEPTIONS_ERROR_GPRSIZE 0x0503 EXCEPTIONS_ERROR_PMISALIGN: EXCEPTIONS_ERROR_PMISALIGN 0x0504 EXCEPTIONS_ERROR_POUTOFMEM: EXCEPTIONS_ERROR_POUTOFMEM 0x0505 EXCEPTIONS_ERROR_PEXECUTE: EXCEPTIONS_ERROR_PEXECUTE 0x0506 EXCEPTIONS_ERROR_DMISALIGN: EXCEPTIONS_ERROR_DMISALIGN 0x0507 EXCEPTIONS_ERROR_DOUTOFMEM: EXCEPTIONS_ERROR_DOUTOFMEM 0x0508 EXCEPTIONS_ERROR_DREAD: EXCEPTIONS_ERROR_DREAD 0x0509 EXCEPTIONS_ERROR_DWRITE: EXCEPTIONS_ERROR_DWRITE 0x050A EXCEPTIONS_ERROR_PSYSERR: EXCEPTIONS_ERROR_PSYSERR 0x050B EXCEPTIONS_ERROR_OVERFLOW: EXCEPTIONS_ERROR_OVERFLOW 0x050C EXCEPTIONS_ERROR_UNKNOWN: EXCEPTIONS_ERROR_UNKNOWN 0x0600 CRCCCITT_BASE_ERROR: CRCCCITT_BASE_ERROR 0x0700 MULTICROPPER_BASE_ERROR: MULTICROPPER_BASE_ERROR 0x0800 DEFINES_I3C_PAD_COMMS_DRIVE_ERROR: DEFINES_I3C_PAD_COMMS_DRIVE_ERROR 0x0A00 DEFINES_VTIMING_LONG_COARSE_MAX_ERROR: DEFINES_VTIMING_LONG_COARSE_MAX_ERROR 0x0A01 DEFINES_VTIMING_LONG_COARSE_MIN_ERROR: DEFINES_VTIMING_LONG_COARSE_MIN_ERROR 0x0A02 DEFINES_VTIMING_LONG_COARSE_IR_MAX_ERROR: DEFINES_VTIMING_LONG_COARSE_IR_MAX_ERROR 0x0A03 DEFINES_VTIMING_LONG_COARSE_IR_MIN_ERROR: DEFINES_VTIMING_LONG_COARSE_IR_MIN_ERROR 0x0A04 DEFINES_VTIMING_BAD_FRAME_LENGTH_ERROR: DEFINES_VTIMING_BAD_FRAME_LENGTH_ERROR 0x0A05 DEFINES_VTIMING_ISB_LONG_PIPE_OVERFLOW: DEFINES_VTIMING_ISB_LONG_PIPE_OVERFLOW 0x0A06 DEFINES_VTIMING_Y_SIZE_SS_ERROR: DEFINES_VTIMING_Y_SIZE_SS_ERROR 0x0A07 DEFINES_VTIMING_X_SIZE_SS_ERROR: DEFINES_VTIMING_X_SIZE_SS_ERROR 0x0A08 DEFINES_VTIMING_BGISON_LOW: DEFINES_VTIMING_BGISON_LOW 0x0A09 DEFINES_VTIMING_BGISON_HIGH: DEFINES_VTIMING_BGISON_HIGH 0x0A0A DEFINES_VTIMING_TOKEN_NOT_FOUND_ERROR: DEFINES_VTIMING_TOKEN_NOT_FOUND_ERROR 0x0B00 DEFINES_ISP_SDR_FIFO_FULL_ERROR: DEFINES_ISP_SDR_FIFO_FULL_ERROR 0x0B01 DEFINES_ISP_ISLGEN_INVALID_CFG_ERROR: DEFINES_ISP_ISLGEN_INVALID_CFG_ERROR 0x0B02 DEFINES_ISP_ISLGEN_MEMORY_LOCKED_ERROR: DEFINES_ISP_ISLGEN_MEMORY_LOCKED_ERROR 0x0B03 DEFINES_ISP_ISLGEN_MISSED_TRIGGER_ERROR: DEFINES_ISP_ISLGEN_MISSED_TRIGGER_ERROR 0x0B04 DEFINES_ISP_ISLGEN_TOO_MANY_ENTRIES_ERROR: DEFINES_ISP_ISLGEN_TOO_MANY_ENTRIES_ERROR 0x0B05 DEFINES_ISP_MULTICROP_NO_ROI_ERROR: DEFINES_ISP_MULTICROP_NO_ROI_ERROR 0x0B06 DEFINES_ISP_ISB2IDP_LINEBLANKING_ERROR: DEFINES_ISP_ISB2IDP_LINEBLANKING_ERROR 0x0B07 DEFINES_ISP_CHANNELSTATS_CHANNEL_INDEX_ERROR: DEFINES_ISP_CHANNELSTATS_CHANNEL_INDEX_ERROR 0x0B08 DEFINES_ISP_CHANNELSTATS_ROI_ERROR: DEFINES_ISP_CHANNELSTATS_ROI_ERROR 0x0B09 DEFINES_ISP_CHANNELSTATS_STATS_OV_ERROR: DEFINES_ISP_CHANNELSTATS_STATS_OV_ERROR 0x0B0A DEFINES_ISP_PATGEN_ERROR_INVALID_PATTERN: DEFINES_ISP_PATGEN_ERROR_INVALID_PATTERN 0x0B0B DEFINES_ISP_X_Y_ERROR_INVALID_XY_CONFIG: DEFINES_ISP_X_Y_ERROR_INVALID_XY_CONFIG 0x0B0C DEFINES_ISP_CHANNELSTATS_PATTERN_ERROR: DEFINES_ISP_CHANNELSTATS_PATTERN_ERROR 0x0B0D DEFINES_ISP_EXPOSURE_USE_CASE_ERROR: DEFINES_ISP_EXPOSURE_USE_CASE_ERROR 0x0C00 DEFINES_OIF_CSI_LANE_DESYNC_ERROR: DEFINES_OIF_CSI_LANE_DESYNC_ERROR 0x0C01 DEFINES_OIF_CSI_PKT_TOO_LONG_ERROR: DEFINES_OIF_CSI_PKT_TOO_LONG_ERROR 0x0C02 DEFINES_OIF_CSI_PKT_TOO_SHORT_ERROR: DEFINES_OIF_CSI_PKT_TOO_SHORT_ERROR 0x0C03 DEFINES_OIF_CSI_UNDERFLOW_ERROR: DEFINES_OIF_CSI_UNDERFLOW_ERROR 0x0C04 DEFINES_OIF_MERGER_EXT_SYNC_MISSED_ERROR: DEFINES_OIF_MERGER_EXT_SYNC_MISSED_ERROR 0x0C05 DEFINES_OIF_ISB2T1_UNDERFLOW: DEFINES_OIF_ISB2T1_UNDERFLOW 0x0C06 DEFINES_OIF_I3CRDOUT_CONFIG_ERROR: DEFINES_OIF_I3CRDOUT_CONFIG_ERROR 0x0C07 DEFINES_OIF_I3CRDOUT_IBI_ERROR: DEFINES_OIF_I3CRDOUT_IBI_ERROR 0x0D00 DEFINES_GENERIC_BAD_PARAM_NVM_CTRL: DEFINES_GENERIC_BAD_PARAM_NVM_CTRL |
RO - - |
0x0000 |
6
|
Description |
: Firmware patch in used |
|
Offset |
: 0x12 |
|
Absolute Address |
: 0x012 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
MAJOR_REVISION |
MINOR_REVISION |
||||||||||||||
|
RO - 0x00 |
RO - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
MAJOR_REVISION |
Major FWP revision |
RO - - |
0x00 |
|
7:0 |
MINOR_REVISION |
Minor FWP revision |
RO - - |
0x00 |
6
|
Description |
: Read-Pattern Vtiming revision |
|
Offset |
: 0x14 |
|
Absolute Address |
: 0x014 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VTRAM_UPDATED |
|
LDEC |
|||||||||||||
|
RO - 0x0 |
|
RO - 0x00 |
|||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
PATTERN |
||||||||||||||
|
RO - 0x00 |
RO - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31 |
VTRAM_UPDATED |
VTRAM update status in case of a manual update |
RO - - |
0x0 |
|
23:16 |
LDEC |
Line decoder timing version |
RO - - |
0x00 |
|
15:8 |
RESERVED0 |
Reserved |
RO - - |
0x00 |
|
7:0 |
PATTERN |
RD pattern timing version |
RO - - |
0x00 |
6
|
Description |
: Global Reset-Pattern Vtiming revision |
|
Offset |
: 0x18 |
|
Absolute Address |
: 0x018 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
PATTERN |
||||||||||||||
|
RO - 0x00 |
RO - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
RESERVED0 |
Reserved |
RO - - |
0x00 |
|
7:0 |
PATTERN |
GR pattern timing version |
RO - - |
0x00 |
6
|
Description |
: Global Transfer-Sequence Vtiming revision |
|
Offset |
: 0x1A |
|
Absolute Address |
: 0x01A |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
PATTERN |
||||||||||||||
|
RO - 0x00 |
RO - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
RESERVED0 |
Reserved |
RO - - |
0x00 |
|
7:0 |
PATTERN |
GT pattern timing version |
RO - - |
0x00 |
6
|
Description |
: Sensor system FSM status |
|
Offset |
: 0x1C |
|
Absolute Address |
: 0x01C |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
|
VALUE |
|||||||||||||
|
RO - 0x0 |
|
RO - 0x01 |
|||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15 |
RESERVED0 |
Reserved |
RO - - |
0x0 |
|
7:0 |
VALUE |
Sensor system FSM status 0x00 HW_STBY: HW_STBY 0x01 READY_TO_BOOT: READY_TO_BOOT 0x02 SW_STBY: SW_STBY 0x03 STREAMING: STREAMING 0x04 STREAMING_AWU_MODE: STREAMING_AWU_MODE 0xAA FW_STALL: FW_STALL 0xFF ERROR: ERROR |
RO - - |
0x01 |
6
|
Description |
: NVM status |
|
Offset |
: 0x1E |
|
Absolute Address |
: 0x01E |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
DRIVER_FSM |
ECC_ERROR |
|
READ_FAIL |
READ_OK |
PROG_FAIL |
PROG_OK |
||||||||
|
RO - 0x00 |
RO - 0x0 |
RO - 0x0 |
|
RO - 0x0 |
RO - 0x0 |
RO - 0x0 |
RO - 0x0 |
||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
RESERVED0 |
Reserved |
RO - - |
0x00 |
|
7:6 |
DRIVER_FSM |
NVM driver FSM 0x00 IDLE: IDLE 0x01 PROG_OP: PROG_OP 0x02 READ_OP: READ_OP 0x03 ERROR: ERROR |
RO - - |
0x0 |
|
5 |
ECC_ERROR |
ECC error detection 0x0 NO_ERROR: NO_ERROR 0x1 ECC_ERROR: ECC_ERROR |
RO - - |
0x0 |
|
3 |
READ_FAIL |
Error during a read operation |
RO - - |
0x0 |
|
2 |
READ_OK |
Successful read operation |
RO - - |
0x0 |
|
1 |
PROG_FAIL |
Error during a program operation |
RO - - |
0x0 |
|
0 |
PROG_OK |
Successful program operation |
RO - - |
0x0 |
6
|
Description |
: Integer part of the external clock frequency in Hz |
|
Offset |
: 0x28 |
|
Absolute Address |
: 0x028 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Integer part of the external clock frequency in Hz |
RO - - |
0x0000 0000 |
6
|
Description |
: PLL output frequency in Hz |
|
Offset |
: 0x2C |
|
Absolute Address |
: 0x02C |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
PLL output frequency in Hz |
RO - - |
0x0000 0000 |
6
|
Description |
: Pixel clock frequency in Hz |
|
Offset |
: 0x30 |
|
Absolute Address |
: 0x030 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Pixel clock frequency in Hz |
RO - - |
0x0000 0000 |
6
|
Description |
: MCU clock frequency in Hz |
|
Offset |
: 0x34 |
|
Absolute Address |
: 0x034 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
MCU clock frequency in Hz |
RO - - |
0x0000 0000 |
6
|
Description |
: PLL multiplier value |
|
Offset |
: 0x38 |
|
Absolute Address |
: 0x038 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RO - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
PLL multiplier value |
RO - - |
0x00 |
6
|
Description |
: Error detected in the clock tree |
|
Offset |
: 0x39 |
|
Absolute Address |
: 0x039 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
CLK_ERR_THSENS |
CLK_ERR_ESC |
CLK_ERR_NVM |
CLK_ERR_HOST |
CLK_ERR_CPNEG |
CLK_ERR_CPPOS |
CLK_ERR_COUNTER |
CLK_ERR_PIX |
|
RO - 0x0 |
RO - 0x0 |
RO - 0x0 |
RO - 0x0 |
RO - 0x0 |
RO - 0x0 |
RO - 0x0 |
RO - 0x0 |
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7 |
CLK_ERR_THSENS |
Bit 7: CLK_ERR_THSENS = 0 if 125 kHz ≤ CLK_ERR_THSENS ≤ 250 kHz |
RO - - |
0x0 |
|
6 |
CLK_ERR_ESC |
Bit 6: CLK_ERR_ESC = 0 if CLK_ERR_ESC ≤ 20 MHz |
RO - - |
0x0 |
|
5 |
CLK_ERR_NVM |
Bit 5: CLK_ERR_NVM = 0 if 10 MHz ≤ CLK_ERR_NVM ≤ 67 MHz. All other situations = 1 |
RO - - |
0x0 |
|
4 |
CLK_ERR_HOST |
Bit 4, CLK_ERR_HOST = 0 if CLK_ERR_HOST ≤ 175 MHz. All other situations = 1. |
RO - - |
0x0 |
|
3 |
CLK_ERR_CPNEG |
Bit 3, CLK_ERR_CPNEG = 0 if 150 MHz ≤ CLK_ERR_CPNEG ≤ 161 MHz. All other situations = 1. |
RO - - |
0x0 |
|
2 |
CLK_ERR_CPPOS |
Bit 2, CLK_ERR_CPPOS = 0 if 400 MHz ≤ CLK_ERR_CPPOS ≤ 500 MHz. All other situations = 1 |
RO - - |
0x0 |
|
1 |
CLK_ERR_COUNTER |
Bit 1, CLK_ERR_COUNTER = 0 if CLK_ERR_COUNTER ≤ 400 MHz. All other situations = 1. |
RO - - |
0x0 |
|
0 |
CLK_ERR_PIX |
Bit 0, CLK_ERR_PIX = 0 if CLK_ERR_COUNTER/CLK_ERR_PIX ≥ 8/3. All other situations = 1. |
RO - - |
0x0 |
6
|
Description |
: Address used for I2C/I3C |
|
Offset |
: 0x3A |
|
Absolute Address |
: 0x03A |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
DEVICE_ID |
|
||||||||||||||
|
RO - 0x0010 |
|
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:1 |
DEVICE_ID |
Device I3C address |
RO - - |
0x0010 |
6
|
Description |
: Last temperature measured with the thermal sensor |
|
Offset |
: 0x3C |
|
Absolute Address |
: 0x03C |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
TH_DEGREE_INT |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
TH_DEGREE_INT |
Temperature in Celcius |
RO - - |
0x0000 |
6
|
Description |
: Frame rate |
|
Offset |
: 0x3E |
|
Absolute Address |
: 0x03E |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Frame rate in FP12.4 |
RO - - |
0x0000 |
6
|
Description |
: Global frame counter |
|
Offset |
: 0x40 |
|
Absolute Address |
: 0x040 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Frame counter over all contexts |
RO - - |
0x0000 |
6
Register: CONTEXT_FRAME_COUNTER
|
Description |
: Context frame counter |
|
Offset |
: 0x42 |
|
Absolute Address |
: 0x042 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Frame counter for the context in use |
RO - - |
0x0000 |
6
Register: CONTEXT_REPEAT_COUNT
|
Description |
: Number of frames for the context in use |
|
Offset |
: 0x44 |
|
Absolute Address |
: 0x044 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Number of frames for the context in use |
RO - - |
0x0000 |
6
|
Description |
: Current context |
|
Offset |
: 0x46 |
|
Absolute Address |
: 0x046 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RO - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Current context |
RO - - |
0x00 |
6
|
Description |
: The next context to be streamed after a RepeatCount number of frames are streamed out |
|
Offset |
: 0x47 |
|
Absolute Address |
: 0x047 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RO - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
The next context to be streamed after a RepeatCount number of frames are streamed out. If this register carries a value > 3, the FW performs a stop streaming operation, after streaming the frames equal to the number stipulated in the RepeatCount register. |
RO - - |
0x00 |
6
|
Description |
: Image orientation |
|
Offset |
: 0x48 |
|
Absolute Address |
: 0x048 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
MODE |
||||||||||||||
|
RO - 0x0000 |
RO - 0x0 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:2 |
RESERVED0 |
Reserved |
RO - - |
0x0000 |
|
1:0 |
MODE |
Image orientation mode control 0x0 NORMAL: = no flip 0x1 X_FLIP: = X flip 0x2 Y_FLIP: = Y flip 0x3 XY_FLIP: = XY flip |
RO - - |
0x0 |
6
|
Description |
: Video timing controls |
|
Offset |
: 0x4A |
|
Absolute Address |
: 0x04A |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
ADC_MODE |
SYNC_MODE |
|||||
|
|
RO - 0x0 |
RO - 0x0 |
|||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
2 |
ADC_MODE |
Video timing ADC mode 9 or 10 bits 0x0 STD_10: = standard mode with 10 bits 0x1 FAST_09: = fast mode with 9 bits |
RO - - |
0x0 |
|
1:0 |
SYNC_MODE |
Video timing synchronization mode 0x0 MASTER: = master mode 0x1 SLAVE_MODE: = streaming on EXTSYNC pulses 0x2 SLAVE_I3C: = streaming on I3C pulses |
RO - - |
0x0 |
6
|
Description |
: Frame output format control |
|
Offset |
: 0x4B |
|
Absolute Address |
: 0x04B |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
OUT_FORMAT |
||||||
|
|
RO - 0x00 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
4:0 |
OUT_FORMAT |
Frame output format control 0x8 RAW8: RAW8 0xA RAW10: RAW10 |
RO - - |
0x00 |
6
|
Description |
: Configuration of the output interface |
|
Offset |
: 0x4C |
|
Absolute Address |
: 0x04C |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED2 |
DATALANE0_SWAP |
RESERVED1 |
CLKLANE_SWAP |
RESERVED0 |
|||||||||||
|
RO - 0x000 |
RO - 0x0 |
RO - 0x0 |
RO - 0x0 |
RO - 0x0 |
|||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:7 |
RESERVED2 |
Reserved |
RO - - |
0x000 |
|
6 |
DATALANE0_SWAP |
Lane swapping 0x0 NO_SWAP: NO_SWAP 0x1 LANE_SWAP: LANE_SWAP |
RO - - |
0x0 |
|
5:4 |
RESERVED1 |
Reserved |
RO - - |
0x0 |
|
3 |
CLKLANE_SWAP |
Clock lane swapping 0x0 NO_SWAP: NO_SWAP 0x1 LANE_SWAP: LANE_SWAP |
RO - - |
0x0 |
|
2:0 |
RESERVED0 |
Reserved |
RO - - |
0x0 |
6
|
Description |
: Virtual channel |
|
Offset |
: 0x4E |
|
Absolute Address |
: 0x04E |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
ISL |
ACTIVE_PIX |
|||||
|
|
RO - 0x0 |
RO - 0x0 |
|||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
3:2 |
ISL |
Virtual channel selection for ISL |
RO - - |
0x0 |
|
1:0 |
ACTIVE_PIX |
Virtual channel selection for image |
RO - - |
0x0 |
6
|
Description |
: Data type for the image data |
|
Offset |
: 0x4F |
|
Absolute Address |
: 0x04F |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
DATA_TYPE |
||||||
|
|
RO - 0x00 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
5:0 |
DATA_TYPE |
Data type selection aligned with RAW format |
RO - - |
0x00 |
6
|
Description |
: Data type for ISL |
|
Offset |
: 0x50 |
|
Absolute Address |
: 0x050 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
DATA_TYPE |
||||||
|
|
RO - 0x00 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
5:0 |
DATA_TYPE |
Data type selection |
RO - - |
0x00 |
6
|
Description |
: PLL status |
|
Offset |
: 0x51 |
|
Absolute Address |
: 0x051 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
SYSTEM_CLOCK_EXT_VS_PLL |
PLL_LOCK |
|||||
|
|
RO - 0x0 |
RO - 0x0 |
|||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
2 |
SYSTEM_CLOCK_EXT_VS_PLL |
System clock driven by 0x0 EXTERNAL: EXTERNAL 0x1 PLL: PLL |
RO - - |
0x0 |
|
1:0 |
PLL_LOCK |
PLL lock status 0x0 UNLOCK: UNLOCK 0x1 WAITING_FOR_LOCK: WAITING_FOR_LOCK 0x2 LOCK: LOCK |
RO - - |
0x0 |
6
|
Description |
: Pattern generator control |
|
Offset |
: 0x52 |
|
Absolute Address |
: 0x052 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
TYPE |
|
ENABLE |
||||||||||||
|
|
RO - 0x00 |
|
RO - 0x0 |
||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
9:4 |
TYPE |
0x22 DGREY: = diagonal grayscale 0x28 PN28: = pseudo random |
RO - - |
0x00 |
|
1:0 |
ENABLE |
Patgen configuration 0x00 BYPASS: BYPASS 0x01 PATGEN_NORMAL: PATGEN_NORMAL |
RO - - |
0x0 |
6
Register: VT_COARSE_EXP_LINES_A
|
Description |
: Applied coarse integration lines A |
|
Offset |
: 0x54 |
|
Absolute Address |
: 0x054 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Coarse integration lines A |
RO - - |
0x0000 |
6
|
Description |
: Applied analog gain |
|
Offset |
: 0x56 |
|
Absolute Address |
: 0x056 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
VALUE |
||||||||||||||
|
RO - 0x000 |
RO - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:5 |
RESERVED0 |
Reserved |
RO - - |
0x000 |
|
4:0 |
VALUE |
0x00 AnalogGain_AGAIN_1: AnalogGain_AGAIN_1 0x01 AnalogGain_AGAIN_1_03: AnalogGain_AGAIN_1_03 0x02 AnalogGain_AGAIN_1_07: AnalogGain_AGAIN_1_07 0x03 AnalogGain_AGAIN_1_1: AnalogGain_AGAIN_1_1 0x04 AnalogGain_AGAIN_1_14: AnalogGain_AGAIN_1_14 0x05 AnalogGain_AGAIN_1_19: AnalogGain_AGAIN_1_19 0x06 AnalogGain_AGAIN_1_23: AnalogGain_AGAIN_1_23 0x07 AnalogGain_AGAIN_1_28: AnalogGain_AGAIN_1_28 0x08 AnalogGain_AGAIN_1_33: AnalogGain_AGAIN_1_33 0x09 AnalogGain_AGAIN_1_39: AnalogGain_AGAIN_1_39 0x0A AnalogGain_AGAIN_1_45: AnalogGain_AGAIN_1_45 0x0B AnalogGain_AGAIN_1_52: AnalogGain_AGAIN_1_52 0x0C AnalogGain_AGAIN_1_6: AnalogGain_AGAIN_1_6 0x0D AnalogGain_AGAIN_1_68: AnalogGain_AGAIN_1_68 0x0E AnalogGain_AGAIN_1_78: AnalogGain_AGAIN_1_78 0x0F AnalogGain_AGAIN_1_88: AnalogGain_AGAIN_1_88 0x10 AnalogGain_AGAIN_2: AnalogGain_AGAIN_2 0x11 AnalogGain_AGAIN_2_13: AnalogGain_AGAIN_2_13 0x12 AnalogGain_AGAIN_2_29: AnalogGain_AGAIN_2_29 0x13 AnalogGain_AGAIN_2_46: AnalogGain_AGAIN_2_46 0x14 AnalogGain_AGAIN_2_67: AnalogGain_AGAIN_2_67 0x15 AnalogGain_AGAIN_2_91: AnalogGain_AGAIN_2_91 0x16 AnalogGain_AGAIN_3_2: AnalogGain_AGAIN_3_2 0x17 AnalogGain_AGAIN_3_56: AnalogGain_AGAIN_3_56 0x18 AnalogGain_AGAIN_4: AnalogGain_AGAIN_4 0x19 AnalogGain_AGAIN_4_57: AnalogGain_AGAIN_4_57 0x1A AnalogGain_AGAIN_5_33: AnalogGain_AGAIN_5_33 0x1B AnalogGain_AGAIN_6_4: AnalogGain_AGAIN_6_4 0x1C AnalogGain_AGAIN_8: AnalogGain_AGAIN_8 |
RO - - |
0x00 |
6
Register: ISP_DIGITAL_GAIN_CH0
|
Description |
: Digital gain, applied from the exposure algorithm channel 0 |
|
Offset |
: 0x58 |
|
Absolute Address |
: 0x058 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RO - 0x00 |
RO - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Digital gain, applied from the exposure algorithm channel 0. Note that the integer part is in 5.8 fixed point format. |
RO - - |
0x00 |
|
7:0 |
FRACT |
Digital gain, applied from the exposure algorithm channel 0. Note that the fractional part is in 5.8 fixed point format. |
RO - - |
0x00 |
6
|
Description |
: Exposure mode control |
|
Offset |
: 0x60 |
|
Absolute Address |
: 0x060 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
MODE |
||||||
|
|
RO - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
2:0 |
MODE |
Exposure mode control 0x0 AUTO_MEAN: = automatic mode 0x1 FREEZE: = freeze AE with currentt settings 0x2 MANUAL: = manual setting mode 0x4 BYPASS: BYPASS |
RO - - |
0x0 |
6
|
Description |
: Status of the auto exposure A |
|
Offset |
: 0x61 |
|
Absolute Address |
: 0x061 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
STATUS |
||||||
|
|
RO - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
0 |
STATUS |
0x0 UNSTABLE: UNSTABLE 0x1 STABLE: STABLE |
RO - - |
0x0 |
6
Register: EXPOSURE_MEAN_ENERGY_A
|
Description |
: Mean energy of the input image for the auto exposure A |
|
Offset |
: 0x62 |
|
Absolute Address |
: 0x062 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RO - 0x00 |
RO - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Mean energy of the input image (integer part) |
RO - - |
0x00 |
|
7:0 |
FRACT |
Mean energy of the input image (fractional part) |
RO - - |
0x00 |
6
|
Description |
: Applied line length |
|
Offset |
: 0x64 |
|
Absolute Address |
: 0x064 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Line length output from the sensor (including the line blanking) |
RO - - |
0x0000 |
6
Register: ISP_EXPOSURE_DIGITAL_GAIN
|
Description |
: Digital gain, computed by the exposure in automatic mode |
|
Offset |
: 0x66 |
|
Absolute Address |
: 0x066 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RO - 0x00 |
RO - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Digital gain, computed by the exposure in automatic mode. This gain does not include white balance gains. It represents only the integer part of the gain in fixed point format. |
RO - - |
0x00 |
|
7:0 |
FRACT |
Digital gain, computed by the exposure in automatic mode. This gain does not include white balance gains. It represents only the fractional part of the gain in fixed point format. |
RO - - |
0x00 |
6
|
Description |
: Applied frame length |
|
Offset |
: 0x68 |
|
Absolute Address |
: 0x068 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Frame length as programmed in the sensor (in 12.4 fixed point format) |
RO - - |
0x0000 0000 |
6
|
Description |
: Image X start from the video timing |
|
Offset |
: 0x6C |
|
Absolute Address |
: 0x06C |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Image X start from the video timing |
RO - - |
0x0000 |
6
|
Description |
: Image X end from the video timing |
|
Offset |
: 0x6E |
|
Absolute Address |
: 0x06E |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Image X end from the video timing |
RO - - |
0x0000 |
6
|
Description |
: Image Y start from the video timing |
|
Offset |
: 0x70 |
|
Absolute Address |
: 0x070 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Image Y start from the video timing |
RO - - |
0x0000 |
6
|
Description |
: Image Y end from the video timing |
|
Offset |
: 0x72 |
|
Absolute Address |
: 0x072 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Image Y end from the video timing |
RO - - |
0x0000 |
6
|
Description |
: Image X size |
|
Offset |
: 0x74 |
|
Absolute Address |
: 0x074 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Image X size |
RO - - |
0x0000 |
6
|
Description |
: Image Y size |
|
Offset |
: 0x76 |
|
Absolute Address |
: 0x076 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Image Y size |
RO - - |
0x0000 |
6
|
Description |
: Streaming readout mode control |
|
Offset |
: 0x78 |
|
Absolute Address |
: 0x078 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
CFG |
||||||||||||||
|
RO - 0x0000 |
RO - 0x0 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:3 |
RESERVED0 |
Reserved |
RO - - |
0x0000 |
|
2:0 |
CFG |
Streaming readout mode control 0x00 NORMAL: = normal streaming 0x01 DBIN_X2: = digital binning x2 0x02 DBIN_X4: = digital binning x4 0x03 SS_X2: = subsampling x2 0x04 SS_X4: = subsampling x4 0x05 SS_X8: = subsampling x8 0x06 XYBIN_X2: = XY binning x2 |
RO - - |
0x0 |
6
|
Description |
: Wait time before the next frame, and blanking in lines |
|
Offset |
: 0x7A |
|
Absolute Address |
: 0x07A |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Wait time before the next frame, and blanking in lines |
RO - - |
0x0000 |
6
Register: EXPOSURE_COARSE_EXP_LINES_B
|
Description |
: Coarse exposure time in lines |
|
Offset |
: 0x7C |
|
Absolute Address |
: 0x07C |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Coarse exposure time in lines |
RO - - |
0x0000 |
6
Register: EXPOSURE_COARSE_EXP_LINES_C
|
Description |
: Coarse exposure time in lines |
|
Offset |
: 0x7E |
|
Absolute Address |
: 0x07E |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Coarse exposure time in lines |
RO - - |
0x0000 |
6
Register: EXPOSURE_MEAN_ENERGY_B
|
Description |
: Mean energy of the input image |
|
Offset |
: 0x80 |
|
Absolute Address |
: 0x080 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RO - 0x00 |
RO - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Mean energy of the input image (integer part) |
RO - - |
0x00 |
|
7:0 |
FRACT |
Mean energy of the input image (fractional part) |
RO - - |
0x00 |
6
Register: EXPOSURE_LIMITS_MINIMUM_COARSE_LINES
|
Description |
: Minimum coarse integration in lines |
|
Offset |
: 0x82 |
|
Absolute Address |
: 0x082 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Minimum coarse integration in lines |
RO - - |
0x0000 |
6
Register: EXPOSURE_LIMITS_MAXIMUM_COARSE_LINES
|
Description |
: Maximum coarse integration in lines |
|
Offset |
: 0x84 |
|
Absolute Address |
: 0x084 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Maximum coarse integration in lines |
RO - - |
0x0000 |
6
Register: DUSTER_DMP_CC_SIGMA_OP
|
Description |
: Damper output of the CC sigma |
|
Offset |
: 0x86 |
|
Absolute Address |
: 0x086 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Damper output of the CC sigma |
RO - - |
0x0000 |
6
|
Description |
: Damper output of the SG threshold output |
|
Offset |
: 0x88 |
|
Absolute Address |
: 0x088 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Damper output of the SG threshold output |
RO - - |
0x0000 |
6
Register: DUSTER_DMP_NOISE_GS_TH1_OP
|
Description |
: Damper output of the GS noise threshold |
|
Offset |
: 0x8A |
|
Absolute Address |
: 0x08A |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Damper output of the GS noise threshold |
RO - - |
0x0000 |
6
Register: DUSTER_DMP_GS_MONO5_TH_OP
|
Description |
: Damper output of the mono5 threshold |
|
Offset |
: 0x8C |
|
Absolute Address |
: 0x08C |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Damper output of the mono5 threshold |
RO - - |
0x0000 |
6
Register: DUSTER_DMP_GS_BLEND_TH_OP
|
Description |
: Damper output of the blend threshold |
|
Offset |
: 0x8E |
|
Absolute Address |
: 0x08E |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Damper output of the blend threshold |
RO - - |
0x0000 |
6
|
Description |
: This register is a marker |
|
Offset |
: 0x90 |
|
Absolute Address |
: 0x090 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RO - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
This register is a marker |
RO - - |
0x00 |
6
|
Description |
: Input GPIO value if input mode is used |
|
Offset |
: 0x91 |
|
Absolute Address |
: 0x091 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RO - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Input GPIO value if input mode is used |
RO - - |
0x00 |
6
|
Description |
: Input GPIO value if input mode is used |
|
Offset |
: 0x92 |
|
Absolute Address |
: 0x092 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RO - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Input GPIO value if input mode is used |
RO - - |
0x00 |
6
|
Description |
: Input GPIO value if input mode is used |
|
Offset |
: 0x93 |
|
Absolute Address |
: 0x093 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RO - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Input GPIO value if input mode is used |
RO - - |
0x00 |
6
|
Description |
: Input GPIO value if input mode is used |
|
Offset |
: 0x94 |
|
Absolute Address |
: 0x094 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RO - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Input GPIO value if input mode is used |
RO - - |
0x00 |
6
|
Description |
: Darck calibration configuration |
|
Offset |
: 0x95 |
|
Absolute Address |
: 0x095 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
NOISE_MASK_BASED_ON_DGAIN |
LEAKYNESS |
ENABLE |
||||
|
|
RO - 0x0 |
RO - 0x0 |
RO - 0x0 |
||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
6 |
NOISE_MASK_BASED_ON_DGAIN |
Noise mask based on digital gain 0x0 FALSE: FALSE 0x1 TRUE: TRUE |
RO - - |
0x0 |
|
5:2 |
LEAKYNESS |
Antecedents of the leaky accumulation process |
RO - - |
0x0 |
|
1:0 |
ENABLE |
DarkCal mode control 0x0 BYPASS: = disable DarkCal 0x1 AUTO: = enable DarkCal in automatic mode 0x2 BYPASS_DARKAVG: = bypass the DarkCal average 0x3 MONO_DARKAVG: = use the DarkCal average for all channels |
RO - - |
0x0 |
6
|
Description |
: Pedestal value used in the DDC block |
|
Offset |
: 0x96 |
|
Absolute Address |
: 0x096 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
VALUE |
||||||||||||||
|
|
RO - 0x000 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
9:0 |
VALUE |
Pedestal value used in the DDC block |
RO - - |
0x000 |
6
|
Description |
: Channel 0 statistics |
|
Offset |
: 0xA8 |
|
Absolute Address |
: 0x0A8 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
|
INTEGER |
||||||||||||||
|
|
RO - 0x000 |
||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RO - 0x000 |
RO - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
17:7 |
INTEGER |
Channel 0 statistics (integer part) |
RO - - |
0x000 |
|
6:0 |
FRACT |
Channel 0 statistics (fractional part) |
RO - - |
0x00 |
6
|
Description |
: Channel 1 statistics |
|
Offset |
: 0xAC |
|
Absolute Address |
: 0x0AC |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
|
INTEGER |
||||||||||||||
|
|
RO - 0x000 |
||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RO - 0x000 |
RO - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
17:7 |
INTEGER |
Channel 1 statistics (integer part) |
RO - - |
0x000 |
|
6:0 |
FRACT |
Channel 1 statistics (fractional part) |
RO - - |
0x00 |
6
|
Description |
: Channel 2 statistics |
|
Offset |
: 0xB0 |
|
Absolute Address |
: 0x0B0 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
|
INTEGER |
||||||||||||||
|
|
RO - 0x000 |
||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RO - 0x000 |
RO - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
17:7 |
INTEGER |
Channel 2 statistics (integer part) |
RO - - |
0x000 |
|
6:0 |
FRACT |
Channel 2 statistics (fractional part) |
RO - - |
0x00 |
6
|
Description |
: Channel 3 statistics |
|
Offset |
: 0xB4 |
|
Absolute Address |
: 0x0B4 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
|
INTEGER |
||||||||||||||
|
|
RO - 0x000 |
||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RO - 0x000 |
RO - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
17:7 |
INTEGER |
Channel 3 statistics (integer part) |
RO - - |
0x000 |
|
6:0 |
FRACT |
Channel 3 statistics (fractional part) |
RO - - |
0x00 |
6
|
Description |
: Time for start up |
|
Offset |
: 0xB8 |
|
Absolute Address |
: 0x0B8 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Time for start up |
RO - - |
0x0000 0000 |
6
|
Description |
: Time for boot |
|
Offset |
: 0xBC |
|
Absolute Address |
: 0x0BC |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Time for boot |
RO - - |
0x0000 0000 |
6
|
Description |
: Time for PLL update |
|
Offset |
: 0xC0 |
|
Absolute Address |
: 0x0C0 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Time for PLL update |
RO - - |
0x0000 0000 |
6
|
Description |
: SOF count |
|
Offset |
: 0xC4 |
|
Absolute Address |
: 0x0C4 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
SOF count |
RO - - |
0x0000 0000 |
6
|
Description |
: DarkCal count |
|
Offset |
: 0xC8 |
|
Absolute Address |
: 0x0C8 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
DarkCal count |
RO - - |
0x0000 0000 |
6
|
Description |
: Latch count |
|
Offset |
: 0xCC |
|
Absolute Address |
: 0x0CC |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Latch count |
RO - - |
0x0000 0000 |
6
|
Description |
: EOF IT count |
|
Offset |
: 0xD0 |
|
Absolute Address |
: 0x0D0 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
EOF IT count |
RO - - |
0x0000 0000 |
6
|
Description |
: Latest time for SOF task |
|
Offset |
: 0xD4 |
|
Absolute Address |
: 0x0D4 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Latest time for SOF task |
RO - - |
0x0000 0000 |
6
|
Description |
: Latest time for DarkCal task |
|
Offset |
: 0xD8 |
|
Absolute Address |
: 0x0D8 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Latest time for DarkCal task |
RO - - |
0x0000 0000 |
6
|
Description |
: Latest time for latch task |
|
Offset |
: 0xDC |
|
Absolute Address |
: 0x0DC |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Latest time for latch task |
RO - - |
0x0000 0000 |
6
|
Description |
: Latest time for EOF task |
|
Offset |
: 0xE0 |
|
Absolute Address |
: 0x0E0 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Latest time for EOF task |
RO - - |
0x0000 0000 |
6
|
Description |
: Latest time for EOF task |
|
Offset |
: 0xE4 |
|
Absolute Address |
: 0x0E4 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Latest time for EOF task |
RO - - |
0x0000 0000 |
6
Register: EXPOSURE_COARSE_EXP_LINES_A
|
Description |
: Coarse exposure time in lines |
|
Offset |
: 0xE8 |
|
Absolute Address |
: 0x0E8 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Coarse exposure time in lines |
RO - - |
0x0000 |
6
Register: EXPOSURE_ANALOG_GAIN
|
Description |
: Analog gain used |
|
Offset |
: 0xEA |
|
Absolute Address |
: 0x0EA |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
VALUE |
||||||||||||||
|
RO - 0x000 |
RO - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:5 |
RESERVED0 |
Reserved |
RO - - |
0x000 |
|
4:0 |
VALUE |
0x00 AnalogGain_AGAIN_1: AnalogGain_AGAIN_1 0x01 AnalogGain_AGAIN_1_03: AnalogGain_AGAIN_1_03 0x02 AnalogGain_AGAIN_1_07: AnalogGain_AGAIN_1_07 0x03 AnalogGain_AGAIN_1_1: AnalogGain_AGAIN_1_1 0x04 AnalogGain_AGAIN_1_14: AnalogGain_AGAIN_1_14 0x05 AnalogGain_AGAIN_1_19: AnalogGain_AGAIN_1_19 0x06 AnalogGain_AGAIN_1_23: AnalogGain_AGAIN_1_23 0x07 AnalogGain_AGAIN_1_28: AnalogGain_AGAIN_1_28 0x08 AnalogGain_AGAIN_1_33: AnalogGain_AGAIN_1_33 0x09 AnalogGain_AGAIN_1_39: AnalogGain_AGAIN_1_39 0x0A AnalogGain_AGAIN_1_45: AnalogGain_AGAIN_1_45 0x0B AnalogGain_AGAIN_1_52: AnalogGain_AGAIN_1_52 0x0C AnalogGain_AGAIN_1_6: AnalogGain_AGAIN_1_6 0x0D AnalogGain_AGAIN_1_68: AnalogGain_AGAIN_1_68 0x0E AnalogGain_AGAIN_1_78: AnalogGain_AGAIN_1_78 0x0F AnalogGain_AGAIN_1_88: AnalogGain_AGAIN_1_88 0x10 AnalogGain_AGAIN_2: AnalogGain_AGAIN_2 0x11 AnalogGain_AGAIN_2_13: AnalogGain_AGAIN_2_13 0x12 AnalogGain_AGAIN_2_29: AnalogGain_AGAIN_2_29 0x13 AnalogGain_AGAIN_2_46: AnalogGain_AGAIN_2_46 0x14 AnalogGain_AGAIN_2_67: AnalogGain_AGAIN_2_67 0x15 AnalogGain_AGAIN_2_91: AnalogGain_AGAIN_2_91 0x16 AnalogGain_AGAIN_3_2: AnalogGain_AGAIN_3_2 0x17 AnalogGain_AGAIN_3_56: AnalogGain_AGAIN_3_56 0x18 AnalogGain_AGAIN_4: AnalogGain_AGAIN_4 0x19 AnalogGain_AGAIN_4_57: AnalogGain_AGAIN_4_57 0x1A AnalogGain_AGAIN_5_33: AnalogGain_AGAIN_5_33 0x1B AnalogGain_AGAIN_6_4: AnalogGain_AGAIN_6_4 0x1C AnalogGain_AGAIN_8: AnalogGain_AGAIN_8 |
RO - - |
0x00 |
6
Register: EXPOSURE_DIGITAL_GAIN_CH0
|
Description |
: Digital gain, applied from the exposure algorithm channel 0 |
|
Offset |
: 0xEC |
|
Absolute Address |
: 0x0EC |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RO - 0x00 |
RO - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Digital gain, applied from the exposure algorithm channel 0. Note that the integer part is in 5.8 fixed point format. |
RO - - |
0x00 |
|
7:0 |
FRACT |
Digital gain, applied from the exposure algorithm channel 0. Note that the fractional part is in 5.8 fixed point format. |
RO - - |
0x00 |
6
|
Description |
: Time to run the patch command |
|
Offset |
: 0xF4 |
|
Absolute Address |
: 0x0F4 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Time to run the patch command |
RO - - |
0x0000 0000 |
6
|
Description |
: Counter for IT statistics |
|
Offset |
: 0xF8 |
|
Absolute Address |
: 0x0F8 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Counter for IT statistics |
RO - - |
0x0000 0000 |
6
|
Description |
: Counter for the ISL general statistics |
|
Offset |
: 0xFC |
|
Absolute Address |
: 0x0FC |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Counter for the ISL general statistics |
RO - - |
0x0000 0000 |
6
|
Description |
: Counter for IT point |
|
Offset |
: 0x100 |
|
Absolute Address |
: 0x100 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Counter for IT point |
RO - - |
0x0000 0000 |
6
|
Description |
: Delay between the integration lines |
|
Offset |
: 0x104 |
|
Absolute Address |
: 0x104 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
DELAY |
||||||||||||||
|
|
RO - 0x0000 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
14:0 |
DELAY |
Delay between the integration lines (in lines) |
RO - - |
0x0000 |
6
|
Description |
: FSM streaming status |
|
Offset |
: 0x106 |
|
Absolute Address |
: 0x106 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RO - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
FSM streaming status 0x00 STBY: STBY 0x01 START_STREAM: START_STREAM 0x02 SOF_TASK: SOF_TASK 0x03 DARK_TASK: DARK_TASK 0x04 EOF_TASK: EOF_TASK 0x05 ITPOINT_TASK: ITPOINT_TASK 0x06 LATCH_TASK: LATCH_TASK 0x07 FRAME_BLANKING: FRAME_BLANKING 0x08 WAKEUP_TASK: WAKEUP_TASK 0x09 START_INTEGRATION_COUNTER: START_INTEGRATION_COUNTER 0x0A START_INTEGRATION: START_INTEGRATION 0x0B STOP_STREAM: STOP_STREAM 0x0C WAITING_TRIG: WAITING_TRIG 0x0D CHANNEL_STAT_TASK: CHANNEL_STAT_TASK 0x0E STATS_PROCESSING_TASK: STATS_PROCESSING_TASK 0x0F EXPOSURE_A_RUN_TASK: EXPOSURE_A_RUN_TASK 0x10 EXPOSURE_B_RUN_TASK: EXPOSURE_B_RUN_TASK 0x20 STREAMING: STREAMING 0x21 CONTEXT_CHANGE_FOR_EXPOSURE: CONTEXT_CHANGE_FOR_EXPOSURE 0x22 CONTEXT_CHANGE_FOR_SOC: CONTEXT_CHANGE_FOR_SOC 0x23 CONTEXT_RUNNING: CONTEXT_RUNNING 0x24 STREAMING_ENTER_LOW_POWER: STREAMING_ENTER_LOW_POWER 0x25 STREAMING_LOW_POWER: STREAMING_LOW_POWER 0x26 STREAMING_EXIT_LOW_POWER: STREAMING_EXIT_LOW_POWER 0x27 LOW_POWER_ENTER: LOW_POWER_ENTER 0x28 LOW_POWER: LOW_POWER 0x29 MCU_WAKEUP: MCU_WAKEUP 0x2A WAITING_FOR_VT_START: WAITING_FOR_VT_START 0x2B STREAMING_STOP_DPHY_DOWN_BEGINS: STREAMING_STOP_DPHY_DOWN_BEGINS 0x2C STREAMING_STOP_DPHY_DOWN_COMPLETED: STREAMING_STOP_DPHY_DOWN_COMPLETED 0x2D STREAMING_START_DPHY_UP_BEGINS: STREAMING_START_DPHY_UP_BEGINS 0x2E STREAMING_START_DPHY_UP_COMPLETED: STREAMING_START_DPHY_UP_COMPLETED 0x2F MCU_IDLE: MCU_IDLE 0x30 MCU_RUNNING: MCU_RUNNING 0x31 PRE_LATCH_PROG_IZR2_TASK: PRE_LATCH_PROG_IZR2_TASK |
RO - - |
0x00 |
6
Register: LOW_POWER_MODE_FEASIBLE
|
Description |
: Low power mode feasability |
|
Offset |
: 0x107 |
|
Absolute Address |
: 0x107 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
VALUE |
||||||
|
|
RO - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
0 |
VALUE |
Low power mode feasability 0x0 FALSE: FALSE 0x1 TRUE: TRUE |
RO - - |
0x0 |
6
Register: VT_COARSE_EXP_LINES_B
|
Description |
: Coarse exposure time in lines |
|
Offset |
: 0x128 |
|
Absolute Address |
: 0x128 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Coarse exposure time in lines |
RO - - |
0x0000 |
6
Register: VT_COARSE_EXP_LINES_C
|
Description |
: Coarse exposure time in lines |
|
Offset |
: 0x12A |
|
Absolute Address |
: 0x12A |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Coarse exposure time in lines |
RO - - |
0x0000 |
6
|
Description |
: Auto exposure configuration |
|
Offset |
: 0x12C |
|
Absolute Address |
: 0x12C |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
ENABLE_MULTI_CONTEXT |
MODE |
|||||
|
|
RO - 0x0 |
RO - 0x0 |
|||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
2 |
ENABLE_MULTI_CONTEXT |
Different ROI statistics per context 0x0 FALSE: FALSE 0x1 TRUE: TRUE |
RO - - |
0x0 |
|
1:0 |
MODE |
Select exposure use cases in terms of exposure count and HDR 0x0 SINGLE_EXPOSURE_LDR: SINGLE_EXPOSURE_LDR 0x1 TWO_EXPOSURE_LDR: TWO_EXPOSURE_LDR 0x2 TWO_EXPOSURE_HDR: TWO_EXPOSURE_HDR 0x3 THREE_EXPOSURE_HDR: THREE_EXPOSURE_HDR |
RO - - |
0x0 |
6
|
Description |
: Auto exposure B status |
|
Offset |
: 0x12D |
|
Absolute Address |
: 0x12D |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
STATUS |
||||||
|
|
RO - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
0 |
STATUS |
0x0 UNSTABLE: UNSTABLE 0x1 STABLE: STABLE |
RO - - |
0x0 |
6
Register: EXPOSURE_GROUP_TOKEN
|
Description |
: Exposure token status |
|
Offset |
: 0x12E |
|
Absolute Address |
: 0x12E |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
PROGRAMMED |
STATUS |
||||||
|
RO - 0x0 |
RO - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:4 |
PROGRAMMED |
Programmed value going to the exposure group token registers |
RO - - |
0x0 |
|
3:0 |
STATUS |
Received value coming from the exposure group token registers |
RO - - |
0x0 |
6
|
Description |
: AWU FSM status |
|
Offset |
: 0x12F |
|
Absolute Address |
: 0x12F |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RO - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
AWU FSM status 0x00 AWU_OFF: AWU_OFF 0x01 AWU_CONVERGENCE_RUNNING: AWU_CONVERGENCE_RUNNING 0x02 AWU_CONVERGENCE_DONE: AWU_CONVERGENCE_DONE 0x03 AWU_DETECTION_RUNNING: AWU_DETECTION_RUNNING 0xAA AWU_DETECTION_DONE: AWU_DETECTION_DONE 0xFF AWU_ERROR: AWU_ERROR |
RO - - |
0x00 |
6
Register: CHANNEL_STAT_MEAN_ENERGY_ACC0
|
Description |
: Mean energy of the accumulator 0 |
|
Offset |
: 0x130 |
|
Absolute Address |
: 0x130 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RO - 0x00 |
RO - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Mean energy of the fractional part for accumulator 0 |
RO - - |
0x00 |
|
7:0 |
FRACT |
Mean energy of the integer part for accumulator 0 |
RO - - |
0x00 |
6
Register: CHANNEL_STAT_MEAN_ENERGY_ACC1
|
Description |
: Mean energy of accumulator 1 |
|
Offset |
: 0x132 |
|
Absolute Address |
: 0x132 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RO - 0x00 |
RO - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Mean energy fractional part for accumulator 1 |
RO - - |
0x00 |
|
7:0 |
FRACT |
Mean energy of the integer part for accumulator 1 |
RO - - |
0x00 |
6
Register: CHANNEL_STAT_MEAN_ENERGY_ACC2
|
Description |
: Mean energy of accumulator 2 |
|
Offset |
: 0x134 |
|
Absolute Address |
: 0x134 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RO - 0x00 |
RO - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Mean energy of the fractional part for accumulator 2 |
RO - - |
0x00 |
|
7:0 |
FRACT |
Mean energy of the integer part for accumulator 2 |
RO - - |
0x00 |
6
|
Description |
: Number of dark lines streamed |
|
Offset |
: 0x136 |
|
Absolute Address |
: 0x136 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RO - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Number of dark lines streamed |
RO - - |
0x00 |
6
|
Description |
: PWL status |
|
Offset |
: 0x137 |
|
Absolute Address |
: 0x137 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
LUT_SEL |
ENABLE |
|||||
|
|
RO - 0x0 |
RO - 0x0 |
|||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
2:1 |
LUT_SEL |
PWL status 0x0 DEFAULT0: DEFAULT0 0x1 DEFAULT1: DEFAULT1 0x2 USER0: USER0 0x3 USER1: USER1 |
RO - - |
0x0 |
|
0 |
ENABLE |
0x0 DISABLE: DISABLE 0x1 ENABLE: ENABLE |
RO - - |
0x0 |
6
|
Description |
: Number of defects corrected by DEFCOR |
|
Offset |
: 0x138 |
|
Absolute Address |
: 0x138 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
NO_OF_DEFECTS_CORRECTED |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
NO_OF_DEFECTS_CORRECTED |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
NO_OF_DEFECTS_CORRECTED |
Number of defects corrected by DEFCOR |
RO - - |
0x0000 0000 |
6
Register: ANALOG_READOUT_SETTINGS
|
Description |
: ANALOG_READOUT_SETTINGS register |
|
Offset |
: 0x13C |
|
Absolute Address |
: 0x13C |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
To be decided |
RO - - |
0x0000 0000 |
6
|
Description |
: Manufacturer's ID |
|
Offset |
: 0x140 |
|
Absolute Address |
: 0x140 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0104 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Manufacturer's ID |
RO - - |
0x0104 |
6
|
Description |
: Noise generator configuration registers |
|
Offset |
: 0x142 |
|
Absolute Address |
: 0x142 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RO - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Noise generator configuration registers |
RO - - |
0x00 |
6
Register: AWU_LEARN_DEFINITIVE
|
Description |
: True when the reference levels and standard deviations for the current frame can be trusted |
|
Offset |
: 0x143 |
|
Absolute Address |
: 0x143 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RO - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
True when the reference levels and standard deviations for the current frame can be trusted |
RO - - |
0x00 |
6
|
Description |
: Status of the auto wake up |
|
Offset |
: 0x144 |
|
Absolute Address |
: 0x144 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
RESERVED0 |
DETECTION |
||||||||||||||
|
RO - 0x0000 |
RO - 0x0 |
||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
ZONE_DETECTION |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:17 |
RESERVED0 |
Reserved |
RO - - |
0x0000 |
|
16 |
DETECTION |
Global detection status 0x0 NONE_DETECTED: NONE_DETECTED 0x1 MOTION_DETECTED: MOTION_DETECTED |
RO - - |
0x0 |
|
15:0 |
ZONE_DETECTION |
Detection per zone |
RO - - |
0x0000 |
6
|
Description |
: Delay between two integrations in VT subtraction mode |
|
Offset |
: 0x148 |
|
Absolute Address |
: 0x148 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
RESERVED0 |
VT_SUB_WAIT_PIXELS |
||||||||||||||
|
RO - 0x0 |
RO - 0x0000 |
||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VT_SUB_WAIT_LINES |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:29 |
RESERVED0 |
Reserved |
RO - - |
0x0 |
|
28:16 |
VT_SUB_WAIT_PIXELS |
Delay in pixels (13 bits) between two integrations in VT subtraction mode |
RO - - |
0x0000 |
|
15:0 |
VT_SUB_WAIT_LINES |
Delay in lines between two integrations in VT subtraction mode |
RO - - |
0x0000 |
6
Register: VT_SUB_DIGITAL_OFFSET
|
Description |
: Offset for VT-SUB |
|
Offset |
: 0x14C |
|
Absolute Address |
: 0x14C |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
DIGITAL_OFFSET |
||||||||||||||
|
|
RO - 0x000 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
9:0 |
DIGITAL_OFFSET |
Offset for VT-SUB, which is 512: power(2, bitwidth-1) |
RO - - |
0x000 |
6
|
Description |
: Mode of the video timing |
|
Offset |
: 0x14E |
|
Absolute Address |
: 0x14E |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
MODE |
||||||
|
|
RO - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
0 |
MODE |
Mode 0x0 MULTI_EXPO: MULTI_EXPO 0x1 VT_SUB: VT_SUB |
RO - - |
0x0 |
6
Register: CHANNEL_STATS_STATE_FOR_EXPOSURE
|
Description |
: Channel stat IP status |
|
Offset |
: 0x14F |
|
Absolute Address |
: 0x14F |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RO - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Status 0x0 NONE: NONE 0x1 FIRST_FRAME: FIRST_FRAME 0x2 READY_TO_PROCESS: READY_TO_PROCESS 0x3 SKIPPED: SKIPPED 0x4 COMPLETE: COMPLETE |
RO - - |
0x00 |
6
Register: CHANNEL_STATS_TASK_LAST
|
Description |
: Microcontroller tick counts, which is the executed statistics task of the last channel |
|
Offset |
: 0x150 |
|
Absolute Address |
: 0x150 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Microcontroller tick counts, which is the executed statistics task of the last channel |
RO - - |
0x0000 0000 |
6
|
Description |
: VT start time |
|
Offset |
: 0x154 |
|
Absolute Address |
: 0x154 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
VT start time |
RO - - |
0x0000 0000 |
6
|
Description |
: VT stop time |
|
Offset |
: 0x158 |
|
Absolute Address |
: 0x158 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
VT stop time |
RO - - |
0x0000 0000 |
6
Register: EXPOSURE_STATS_PROCESSING_TIME
|
Description |
: Exposure statistics processing time |
|
Offset |
: 0x15C |
|
Absolute Address |
: 0x15C |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Exposure statistics processing time |
RO - - |
0x0000 0000 |
6
Register: EXPOSURE_A_COMPILER_TIME
|
Description |
: Microcontroller tick counts taken by the exposure A compiler |
|
Offset |
: 0x160 |
|
Absolute Address |
: 0x160 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Microcontroller tick counts taken by the exposure A compiler |
RO - - |
0x0000 0000 |
6
Register: EXPOSURE_B_COMPILER_TIME
|
Description |
: Microcontroller tick counts taken by the exposure B compiler |
|
Offset |
: 0x164 |
|
Absolute Address |
: 0x164 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Microcontroller tick counts taken by the exposure B compiler |
RO - - |
0x0000 0000 |
6
Register: EXPOSURE_RUN_A_START_FRAME
|
Description |
: Frame count when the exposure A compiler runs or starts executing |
|
Offset |
: 0x168 |
|
Absolute Address |
: 0x168 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Frame count when the exposure A compiler runs or starts executing |
RO - - |
0x0000 |
6
Register: EXPOSURE_RUN_A_END_FRAME
|
Description |
: Frame count when the exposure A compiler finishes executing |
|
Offset |
: 0x16A |
|
Absolute Address |
: 0x16A |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Frame count when the exposure A compiler finishes executing |
RO - - |
0x0000 |
6
Register: EXPOSURE_RUN_B_START_FRAME
|
Description |
: Frame count when the exposure B compiler runs or starts executing |
|
Offset |
: 0x16C |
|
Absolute Address |
: 0x16C |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Frame count when the exposure B compiler runs or starts executing |
RO - - |
0x0000 |
6
Register: EXPOSURE_RUN_B_END_FRAME
|
Description |
: Frame count when the exposure B compiler finishes executing |
|
Offset |
: 0x16E |
|
Absolute Address |
: 0x16E |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Frame count when the exposure B compiler finishes executing |
RO - - |
0x0000 |
6
Register: EXPOSURE_PENDING_INTG_ABSORBED
|
Description |
: Flag set when pending exposure is absorbed |
|
Offset |
: 0x170 |
|
Absolute Address |
: 0x170 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
VALUE |
||||||
|
|
RO - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
0 |
VALUE |
Flag set when pending exposure is absorbed |
RO - - |
0x0 |
6
Register: EXPOSURE_ACTIVE_INSTANCE
|
Description |
: Exposure instance used for the actual frame |
|
Offset |
: 0x171 |
|
Absolute Address |
: 0x171 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
VALUE |
||||||
|
|
RO - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
0 |
VALUE |
0x0 EXPOSURE_A: EXPOSURE_A 0x1 EXPOSURE_B: EXPOSURE_B |
RO - - |
0x0 |
6
Register: EXPOSURE_COARSE_INTG_MARGIN
|
Description |
: Coarse exposure integration margin |
|
Offset |
: 0x174 |
|
Absolute Address |
: 0x174 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Coarse exposure integration margin |
RO - - |
0x0000 |
6
Register: EXPOSURE_NON_OVERLAP_LIMIT
|
Description |
: Nonoverlap exposure limit |
|
Offset |
: 0x176 |
|
Absolute Address |
: 0x176 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Nonoverlap exposure limit |
RO - - |
0x0000 |
6
Register: LOW_POWER_INTER_FRAME_COMPUTED
|
Description |
: Time between frames in LP mode |
|
Offset |
: 0x178 |
|
Absolute Address |
: 0x178 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Time between frames in LP mode |
RO - - |
0x0000 0000 |
6
Register: LOW_POWER_TASK_MARGIN_COMPUTED
|
Description |
: Task margin left while in LP mode |
|
Offset |
: 0x17C |
|
Absolute Address |
: 0x17C |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Task margin left while in LP mode |
RO - - |
0x0000 0000 |
6
Register: LOW_POWER_LONGEST_EXPOSURE_SELECTED
|
Description |
: Longest exposure selected in LP mode |
|
Offset |
: 0x180 |
|
Absolute Address |
: 0x180 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Longest exposure selected in LP mode |
RO - - |
0x0000 |
6
Register: EXPOSURE_MAX_COARSE_LINES_VT_SUB_A
|
Description |
: Maximum coarse integration in lines for VT-SUB mode A |
|
Offset |
: 0x182 |
|
Absolute Address |
: 0x182 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Maximum coarse integration in lines for VT-SUB mode (A) |
RO - - |
0x0000 |
6
Register: EXPOSURE_MAX_COARSE_LINES_VT_SUB_B
|
Description |
: Maximum coarse integration in lines for VT-SUB mode B |
|
Offset |
: 0x184 |
|
Absolute Address |
: 0x184 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Maximum coarse integration in lines for VT-SUB mode (B) |
RO - - |
0x0000 |
6
Register: EXPOSURE_MAX_COARSE_LINES_VT_MULTI
|
Description |
: Maximum coarse integration in lines for VT-multi-exposure mode |
|
Offset |
: 0x186 |
|
Absolute Address |
: 0x186 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RO - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Maximum coarse integration in lines for VT-multi-exposure mode |
RO - - |
0x0000 |
6
Block: CMD
|
Description |
: Commands given by Host |
3
|
Description |
: Register to send command in BOOT state |
|
Offset |
: 0x0 |
|
Absolute Address |
: 0x200 |
|
Addressing Mode |
: 8-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
COMMAND |
||||||
|
|
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
1:0 |
COMMAND |
List of commands available in BOOT state 0x0 CMD_ACK: CMD_ACK 0x1 BOOT: BOOT 0x2 PATCH_AND_BOOT: PATCH_AND_BOOT 0x3 DEVICE_COMMS_UPDATE: DEVICE_COMMS_UPDATE |
RW - - |
0x0 |
6
|
Description |
: Register to send command in STBY state |
|
Offset |
: 0x1 |
|
Absolute Address |
: 0x201 |
|
Addressing Mode |
: 8-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
COMMAND |
||||||
|
|
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
3:0 |
COMMAND |
List of commands available in STBY state: 0x0 CMD_ACK: CMD_ACK 0x1 START_STREAM: START_STREAM 0x2 NVM_READ: NVM_READ 0x3 NVM_PROG: NVM_PROG 0x4 THSENS_READ: THSENS_READ 0x5 DEVICE_COMMS_UPDATE: DEVICE_COMMS_UPDATE 0x6 START_VTRAM_UPDATE: START_VTRAM_UPDATE 0x7 END_VTRAM_UPDATE: END_VTRAM_UPDATE 0x8 START_AWU: START_AWU |
RW - - |
0x0 |
6
|
Description |
: Register to send command in STREAMING state |
|
Offset |
: 0x2 |
|
Absolute Address |
: 0x202 |
|
Addressing Mode |
: 8-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
COMMAND |
||||||
|
|
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
3:0 |
COMMAND |
List of commands available in STREAMING state: 0x0 CMD_ACK: CMD_ACK 0x1 STOP_STREAM: STOP_STREAM 0x2 VT_FSYNC_IN_I3C: VT_FSYNC_IN_I3C |
RW - - |
0x0 |
6
Block: SENSOR_SETTINGS
|
Description |
: Setting specific to Wolfy system |
3
|
Description |
: External clock frequency in Hz |
|
Offset |
: 0x0 |
|
Absolute Address |
: 0x220 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x00B7 1B00 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x00B7 1B00 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
External clock frequency in Hz |
RW - - |
0x00B7 1B00 |
6
|
Description |
: PLL MIPI clock frequency in Hz |
|
Offset |
: 0x4 |
|
Absolute Address |
: 0x224 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x4786 8C00 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x4786 8C00 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
PLL MIPI clock frequency in Hz |
RW - - |
0x4786 8C00 |
6
|
Description |
: NVM controls |
|
Offset |
: 0x8 |
|
Absolute Address |
: 0x228 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
ECC_CTRL |
ACCESS_MODE |
|||||
|
|
RW - 0x0 |
RW - 0x0 |
|||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
2 |
ECC_CTRL |
NVM ECC control 0x0 NVM_ECC_ON: NVM_ECC_ON 0x1 NVM_ECC_OFF: NVM_ECC_OFF |
RW - - |
0x0 |
|
1:0 |
ACCESS_MODE |
NVM read/write access mode 0x0 NVM_BURST_MODE: NVM_BURST_MODE 0x1 NVM_SINGLE_MODE: NVM_SINGLE_MODE |
RW - - |
0x0 |
6
|
Description |
: Number of 32-bit words to read/write in burst mode |
|
Offset |
: 0x9 |
|
Absolute Address |
: 0x229 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Number of 32-bit words to read/write in burst mode |
RW - - |
0x00 |
6
|
Description |
: Start address in NVM for read/write burst operation |
|
Offset |
: 0xA |
|
Absolute Address |
: 0x22A |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
VALUE |
||||||||||||||
|
|
RW - 0x000 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
8:0 |
VALUE |
Start address in NVM for read/write burst operation |
RW - - |
0x000 |
6
|
Description |
: I2C and I3C controls |
|
Offset |
: 0x10 |
|
Absolute Address |
: 0x230 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
DRIVE |
DEVICE_ID |
|
||||||||||||
|
|
RW - 0x1 |
RW - 0x10 |
|
||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
10:8 |
DRIVE |
Drive configurations for I2C/I3C pads |
RW - - |
0x1 |
|
7:1 |
DEVICE_ID |
Device I2C address |
RW - - |
0x10 |
6
Block: STREAM_STATICS
|
Description |
: Static setting related to streaming from Wolfy sensor |
3
|
Description |
: Line length configuration |
|
Offset |
: 0x0 |
|
Absolute Address |
: 0x300 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0468 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Line length configuration |
RW - - |
0x0468 |
6
|
Description |
: Image orientation mode control |
|
Offset |
: 0x2 |
|
Absolute Address |
: 0x302 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
|
MODE |
|||||||||||||
|
RW - 0x0 |
|
RW - 0x0 |
|||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
1:0 |
MODE |
Image orientation mode control 0x00 NORMAL: = no flip 0x01 X_FLIP: = X flip 0x02 Y_FLIP: = Y flip 0x03 XY_FLIP: = XY flip |
RW - - |
0x0 |
6
|
Description |
: Patgen configuration |
|
Offset |
: 0x4 |
|
Absolute Address |
: 0x304 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
RESERVED0 |
|
||||||||||||||
|
RW - 0x0 |
|
||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
TYPE |
|
ENABLE |
||||||||||||
|
|
RW - 0x22 |
|
RW - 0x0 |
||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
9:4 |
TYPE |
0x22 DGREY: = diagonal grayscale 0x28 PN28: = pseudo random |
RW - - |
0x22 |
|
1:0 |
ENABLE |
Patgen configuration 0x00 BYPASS: BYPASS 0x01 PATGEN: PATGEN |
RW - - |
0x0 |
6
Register: EXPOSURE_FORCE_COLDSTART
|
Description |
: Force the exposure to start from for the auto exposure |
|
Offset |
: 0x8 |
|
Absolute Address |
: 0x308 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
VALUE |
||||||
|
|
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
0 |
VALUE |
Force the exposure to start from for the auto exposure 0x0 FALSE: FALSE 0x1 TRUE: TRUE |
RW - - |
0x0 |
6
|
Description |
: ADC modes & Synchronization modes |
|
Offset |
: 0x9 |
|
Absolute Address |
: 0x309 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
ADC_MODE |
SYNC_MODE |
|||||
|
|
RW - 0x0 |
RW - 0x0 |
|||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
2 |
ADC_MODE |
Video timing ADC mode 9 or 10 bits 0x0 STD_10: = standard mode with 10 bits 0x1 FAST_09: = fast mode with 9 bits |
RW - - |
0x0 |
|
1:0 |
SYNC_MODE |
Video timing synchronization mode 0x00 MASTER: = master mode 0x01 SLAVE: = streaming on EXTSYNC pulses 0x02 SLAVE_I3C: = streaming on I3C pulses |
RW - - |
0x0 |
6
|
Description |
: Select frame output format between RAW8 and RAW10 |
|
Offset |
: 0xA |
|
Absolute Address |
: 0x30A |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
|
OUT_FORMAT |
|||||||||||||
|
RW - 0x0 |
|
RW - 0x0A |
|||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
4:0 |
OUT_FORMAT |
Frame output format control 0x8 RAW8: RAW8 0xA RAW10: RAW10 |
RW - - |
0x0A |
6
|
Description |
: Control of CSI polarity inversion for data lane and clock lane |
|
Offset |
: 0xC |
|
Absolute Address |
: 0x30C |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
|
DATALANE0_SWAP |
|
CLKLANE_SWAP |
RESERVED2 |
||||||||||
|
RW - 0x0 |
|
RW - 0x0 |
|
RW - 0x0 |
RW - 0x0 |
||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
6 |
DATALANE0_SWAP |
CSI lane 0 swapping 0x0 NO_SWAP: NO_SWAP 0x1 LANE_SWAP: LANE_SWAP |
RW - - |
0x0 |
|
3 |
CLKLANE_SWAP |
CSI clock lane swapping 0x0 NO_SWAP: NO_SWAP 0x1 LANE_SWAP: LANE_SWAP |
RW - - |
0x0 |
|
2:0 |
RESERVED2 |
Reserved |
RW - - |
0x0 |
6
|
Description |
: Virtual channel selection |
|
Offset |
: 0xE |
|
Absolute Address |
: 0x30E |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
ISL |
ACTIVE_PIX |
|||||
|
|
RW - 0x0 |
RW - 0x0 |
|||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
3:2 |
ISL |
Virtual channel selection for ISL |
RW - - |
0x0 |
|
1:0 |
ACTIVE_PIX |
Virtual channel selection for the output image |
RW - - |
0x0 |
6
|
Description |
: CSI data type selection for RAW Image format |
|
Offset |
: 0xF |
|
Absolute Address |
: 0x30F |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
DATA_TYPE |
||||||
|
|
RW - 0x2B |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
5:0 |
DATA_TYPE |
Data type selection for RAW Image format |
RW - - |
0x2B |
6
|
Description |
: CSI data type selection for status lines |
|
Offset |
: 0x10 |
|
Absolute Address |
: 0x310 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
DATA_TYPE |
||||||
|
|
RW - 0x12 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
5:0 |
DATA_TYPE |
Data type selection for status lines |
RW - - |
0x12 |
6
|
Description |
: Enable/disable Ultra-Low Power Mode |
|
Offset |
: 0x11 |
|
Absolute Address |
: 0x311 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
ENABLE |
||||||
|
|
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
0 |
ENABLE |
ULPM enable 0x0 DISABLE: DISABLE 0x1 ENABLE: ENABLE |
RW - - |
0x0 |
6
|
Description |
: Auto exposure use case |
|
Offset |
: 0x12 |
|
Absolute Address |
: 0x312 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
ENABLE_MULTI_CONTEXT |
MODE |
|||||
|
|
RW - 0x0 |
RW - 0x0 |
|||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
2 |
ENABLE_MULTI_CONTEXT |
Different ROI statistics per context 0x0 FALSE: FALSE 0x1 TRUE: TRUE |
RW - - |
0x0 |
|
1:0 |
MODE |
Select exposure use cases in terms of exposure count and HDR 0x0 SINGLE_EXPOSURE_LDR: SINGLE_EXPOSURE_LDR 0x1 TWO_EXPOSURE_LDR: TWO_EXPOSURE_LDR 0x2 TWO_EXPOSURE_HDR: TWO_EXPOSURE_HDR 0x3 THREE_EXPOSURE_HDR: THREE_EXPOSURE_HDR |
RW - - |
0x0 |
6
Register: EXPOSURE_PRIORITY_LONG_VS_SHORT
|
Description |
: Auto exposure priority |
|
Offset |
: 0x13 |
|
Absolute Address |
: 0x313 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
VALUE |
||||||
|
|
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
0 |
VALUE |
This register gives priority to either the long or short exposure. The prioritized exposure is calculated first. The nonprioritized exposure is calculated second, based on the calculation of the prioritized exposure. 0x0 SHORT_EXPO: SHORT_EXPO 0x1 LONG_EXPO: LONG_EXPO |
RW - - |
0x0 |
6
|
Description |
: Enable logarithm log |
|
Offset |
: 0x14 |
|
Absolute Address |
: 0x314 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
ENABLE |
||||||
|
|
RW - 0x1 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
0 |
ENABLE |
0x0 FALSE: FALSE 0x1 TRUE: TRUE |
RW - - |
0x1 |
6
Register: EXPOSURE_MIN_LINES_BW_DIFF_EXPOSURES
|
Description |
: Minimum difference exposure when using double exposure mechanism |
|
Offset |
: 0x15 |
|
Absolute Address |
: 0x315 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RW - 0x05 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Accommodate design limitation of minimum lines, between different exposures, in multi-exposure cases (two exposures must be separated by some minimum constraints). |
RW - - |
0x05 |
6
Register: EXPOSURE_LIMITS_AG_MIN
|
Description |
: Minimum analog gain |
|
Offset |
: 0x16 |
|
Absolute Address |
: 0x316 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
VALUE |
||||||
|
|
RW - 0x00 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
4:0 |
VALUE |
0x00 AnalogGain_AGAIN_1: AnalogGain_AGAIN_1 0x01 AnalogGain_AGAIN_1_03: AnalogGain_AGAIN_1_03 0x02 AnalogGain_AGAIN_1_07: AnalogGain_AGAIN_1_07 0x03 AnalogGain_AGAIN_1_1: AnalogGain_AGAIN_1_1 0x04 AnalogGain_AGAIN_1_14: AnalogGain_AGAIN_1_14 0x05 AnalogGain_AGAIN_1_19: AnalogGain_AGAIN_1_19 0x06 AnalogGain_AGAIN_1_23: AnalogGain_AGAIN_1_23 0x07 AnalogGain_AGAIN_1_28: AnalogGain_AGAIN_1_28 0x08 AnalogGain_AGAIN_1_33: AnalogGain_AGAIN_1_33 0x09 AnalogGain_AGAIN_1_39: AnalogGain_AGAIN_1_39 0x0A AnalogGain_AGAIN_1_45: AnalogGain_AGAIN_1_45 0x0B AnalogGain_AGAIN_1_52: AnalogGain_AGAIN_1_52 0x0C AnalogGain_AGAIN_1_6: AnalogGain_AGAIN_1_6 0x0D AnalogGain_AGAIN_1_68: AnalogGain_AGAIN_1_68 0x0E AnalogGain_AGAIN_1_78: AnalogGain_AGAIN_1_78 0x0F AnalogGain_AGAIN_1_88: AnalogGain_AGAIN_1_88 0x10 AnalogGain_AGAIN_2: AnalogGain_AGAIN_2 0x11 AnalogGain_AGAIN_2_13: AnalogGain_AGAIN_2_13 0x12 AnalogGain_AGAIN_2_29: AnalogGain_AGAIN_2_29 0x13 AnalogGain_AGAIN_2_46: AnalogGain_AGAIN_2_46 0x14 AnalogGain_AGAIN_2_67: AnalogGain_AGAIN_2_67 0x15 AnalogGain_AGAIN_2_91: AnalogGain_AGAIN_2_91 0x16 AnalogGain_AGAIN_3_2: AnalogGain_AGAIN_3_2 0x17 AnalogGain_AGAIN_3_56: AnalogGain_AGAIN_3_56 0x18 AnalogGain_AGAIN_4: AnalogGain_AGAIN_4 0x19 AnalogGain_AGAIN_4_5714: AnalogGain_AGAIN_4_5714 0x1A AnalogGain_AGAIN_5_3333: AnalogGain_AGAIN_5_3333 0x1B AnalogGain_AGAIN_6_4: AnalogGain_AGAIN_6_4 0x1C AnalogGain_AGAIN_8_0: AnalogGain_AGAIN_8_0 |
RW - - |
0x00 |
6
Register: EXPOSURE_LIMITS_AG_MAX
|
Description |
: Maximum analog gain |
|
Offset |
: 0x17 |
|
Absolute Address |
: 0x317 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
VALUE |
||||||
|
|
RW - 0x1C |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
4:0 |
VALUE |
0x00 AnalogGain_AGAIN_1: AnalogGain_AGAIN_1 0x01 AnalogGain_AGAIN_1_03: AnalogGain_AGAIN_1_03 0x02 AnalogGain_AGAIN_1_07: AnalogGain_AGAIN_1_07 0x03 AnalogGain_AGAIN_1_1: AnalogGain_AGAIN_1_1 0x04 AnalogGain_AGAIN_1_14: AnalogGain_AGAIN_1_14 0x05 AnalogGain_AGAIN_1_19: AnalogGain_AGAIN_1_19 0x06 AnalogGain_AGAIN_1_23: AnalogGain_AGAIN_1_23 0x07 AnalogGain_AGAIN_1_28: AnalogGain_AGAIN_1_28 0x08 AnalogGain_AGAIN_1_33: AnalogGain_AGAIN_1_33 0x09 AnalogGain_AGAIN_1_39: AnalogGain_AGAIN_1_39 0x0A AnalogGain_AGAIN_1_45: AnalogGain_AGAIN_1_45 0x0B AnalogGain_AGAIN_1_52: AnalogGain_AGAIN_1_52 0x0C AnalogGain_AGAIN_1_6: AnalogGain_AGAIN_1_6 0x0D AnalogGain_AGAIN_1_68: AnalogGain_AGAIN_1_68 0x0E AnalogGain_AGAIN_1_78: AnalogGain_AGAIN_1_78 0x0F AnalogGain_AGAIN_1_88: AnalogGain_AGAIN_1_88 0x10 AnalogGain_AGAIN_2: AnalogGain_AGAIN_2 0x11 AnalogGain_AGAIN_2_13: AnalogGain_AGAIN_2_13 0x12 AnalogGain_AGAIN_2_29: AnalogGain_AGAIN_2_29 0x13 AnalogGain_AGAIN_2_46: AnalogGain_AGAIN_2_46 0x14 AnalogGain_AGAIN_2_67: AnalogGain_AGAIN_2_67 0x15 AnalogGain_AGAIN_2_91: AnalogGain_AGAIN_2_91 0x16 AnalogGain_AGAIN_3_2: AnalogGain_AGAIN_3_2 0x17 AnalogGain_AGAIN_3_56: AnalogGain_AGAIN_3_56 0x18 AnalogGain_AGAIN_4: AnalogGain_AGAIN_4 0x19 AnalogGain_AGAIN_4_5714: AnalogGain_AGAIN_4_5714 0x1A AnalogGain_AGAIN_5_3333: AnalogGain_AGAIN_5_3333 0x1B AnalogGain_AGAIN_6_4: AnalogGain_AGAIN_6_4 0x1C AnalogGain_AGAIN_8_0: AnalogGain_AGAIN_8_0 |
RW - - |
0x1C |
6
Register: EXPOSURE_LIMITS_DG_MIN
|
Description |
: Minimum digital gain |
|
Offset |
: 0x18 |
|
Absolute Address |
: 0x318 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RW - 0x01 |
RW - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Exposure limits of the digital gain minimum (integer part) |
RW - - |
0x01 |
|
7:0 |
FRACT |
Exposure limits of the digital gain minimum (fractional part) |
RW - - |
0x00 |
6
Register: EXPOSURE_LIMITS_DG_MAX
|
Description |
: Maximum digital gain |
|
Offset |
: 0x1A |
|
Absolute Address |
: 0x31A |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RW - 0x1F |
RW - 0xFF |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Exposure limits of the digital gain maximum (integer part) |
RW - - |
0x1F |
|
7:0 |
FRACT |
Exposure limits of the digital gain maximum (fractional part) |
RW - - |
0xFF |
6
Register: EXPOSURE_HDR_FIX_RATIO
|
Description |
: HDR ratio when in HDr auto exposure mode |
|
Offset |
: 0x1C |
|
Absolute Address |
: 0x31C |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
LONG_TO_MEDIUM |
|||||||||||||||
|
RW - 0x0008 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
MEDIUM_TO_SHORT |
|||||||||||||||
|
RW - 0x0008 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:16 |
LONG_TO_MEDIUM |
HDR gain for exposure_RGB_2 with respect to exposure_RGB_1 |
RW - - |
0x0008 |
|
15:0 |
MEDIUM_TO_SHORT |
HDR gain for exposure_RGB_3 with respect to exposure_RGB_1 |
RW - - |
0x0008 |
6
Register: I3C_FRAME_READOUT_CTRL
|
Description |
: I3C readout configuration |
|
Offset |
: 0x24 |
|
Absolute Address |
: 0x324 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
I3C_PAYLOAD_SIZE |
GPIO_THRESHOLD_MODE |
INTERRUPT_MODE_TO_HOST |
I3C_READOUT_SKIP_HEADER |
ENABLE |
||||||||||
|
RW - 0x0 |
RW - 0x000 |
RW - 0x0 |
RW - 0x0 |
RW - 0x1 |
RW - 0x0 |
||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
14:6 |
I3C_PAYLOAD_SIZE |
Number of bytes per read transaction (if 0, use the current output image width). The value must be a module of 4. |
RW - - |
0x000 |
|
5:3 |
GPIO_THRESHOLD_MODE |
GPIO threshold operating mode 0x0 DEFAULT: DEFAULT 0x1 MODE1: MODE1 0x2 MODE2: MODE2 0x3 MODE3: MODE3 0x4 MODE4: MODE4 |
RW - - |
0x0 |
|
2 |
INTERRUPT_MODE_TO_HOST |
0x0 GPIO: GPIO 0x1 I3C_SLAVE_IBI: I3C_SLAVE_IBI |
RW - - |
0x0 |
|
1 |
I3C_READOUT_SKIP_HEADER |
Skip the SOF/EOF while sending data 0x0 DISABLE: = skip header is disabled 0x1 ENABLE: = skip header is enabled |
RW - - |
0x1 |
|
0 |
ENABLE |
I3C frame readout control 0x0 DISABLE: = I3C frame readout is disabled 0x1 ENABLE: = I3C frame readout is enabled |
RW - - |
0x0 |
6
|
Description |
: Control of the ISL output |
|
Offset |
: 0x26 |
|
Absolute Address |
: 0x326 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
VALUE |
||||||
|
|
RW - 0x1 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
0 |
VALUE |
Output ISL 0x0 Disable: Disable 0x1 Enable: Enable |
RW - - |
0x1 |
6
Register: ISL_PKT_EQ_ACTIVELINE
|
Description |
: Padding of the ISL to the image array |
|
Offset |
: 0x27 |
|
Absolute Address |
: 0x327 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
ENABLE |
|||||||
|
RW - 0x01 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
ENABLE |
0x0 DISABLED: DISABLED 0x1 ENABLED: ENABLED |
RW - - |
0x01 |
6
|
Description |
: Delay of the start integration when in slave mode |
|
Offset |
: 0x28 |
|
Absolute Address |
: 0x328 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Tunable slave mode delay in lines |
RW - - |
0x0000 |
6
|
Description |
: Control of the dark calibration |
|
Offset |
: 0x2A |
|
Absolute Address |
: 0x32A |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
NOISE_MASK_BASED_ON_DGAIN |
LEAKYNESS |
ENABLE |
||||
|
|
RW - 0x1 |
RW - 0x0 |
RW - 0x1 |
||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
6 |
NOISE_MASK_BASED_ON_DGAIN |
Noise mask based on digital gain 0x0 FALSE: FALSE 0x1 TRUE: TRUE |
RW - - |
0x1 |
|
5:2 |
LEAKYNESS |
Antecedent of the leaky accumulation process |
RW - - |
0x0 |
|
1:0 |
ENABLE |
DarkCal mode control 0x0 BYPASS: = disable DarkCal 0x1 AUTO: = enable DarkCal in automatic mode 0x2 BYPASS_DARKAVG: = bypass the DarkCal average 0x3 MONO_DARKAVG: = use the Darkcal average for all channels |
RW - - |
0x1 |
6
|
Description |
: Control of the PWL |
|
Offset |
: 0x2B |
|
Absolute Address |
: 0x32B |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
EXPO_BIAS |
ENABLE |
||||||
|
RW - 0x00 |
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:1 |
EXPO_BIAS |
PWL_VALUE |
RW - - |
0x00 |
|
0 |
ENABLE |
0x0 DISABLE: DISABLE 0x1 ENABLE: ENABLE |
RW - - |
0x0 |
6
|
Description |
: Abscissa 0 |
|
Offset |
: 0x2C |
|
Absolute Address |
: 0x32C |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Abscissa 0 |
RW - - |
0x0000 |
6
|
Description |
: Abscissa 1 |
|
Offset |
: 0x2E |
|
Absolute Address |
: 0x32E |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Abscissa 1 |
RW - - |
0x0000 |
6
|
Description |
: Abscissa 2 |
|
Offset |
: 0x30 |
|
Absolute Address |
: 0x330 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Abscissa 2 |
RW - - |
0x0000 |
6
|
Description |
: Abscissa 3 |
|
Offset |
: 0x32 |
|
Absolute Address |
: 0x332 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Abscissa 3 |
RW - - |
0x0000 |
6
|
Description |
: Ordinate 0 |
|
Offset |
: 0x34 |
|
Absolute Address |
: 0x334 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Ordinate 0 |
RW - - |
0x0000 |
6
|
Description |
: Ordinate 1 |
|
Offset |
: 0x36 |
|
Absolute Address |
: 0x336 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Ordinate 1 |
RW - - |
0x0000 |
6
|
Description |
: Ordinate 2 |
|
Offset |
: 0x38 |
|
Absolute Address |
: 0x338 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Ordinate 2 |
RW - - |
0x0000 |
6
|
Description |
: Ordinate 3 |
|
Offset |
: 0x3A |
|
Absolute Address |
: 0x33A |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Ordinate 3 |
RW - - |
0x0000 |
6
|
Description |
: Gradient 0 |
|
Offset |
: 0x3C |
|
Absolute Address |
: 0x33C |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Gradient 0 |
RW - - |
0x0000 0000 |
6
|
Description |
: Gradient 1 |
|
Offset |
: 0x40 |
|
Absolute Address |
: 0x340 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Gradient 1 |
RW - - |
0x0000 0000 |
6
|
Description |
: Gradient 2 |
|
Offset |
: 0x44 |
|
Absolute Address |
: 0x344 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Gradient 2 |
RW - - |
0x0000 0000 |
6
|
Description |
: Gradient 3 |
|
Offset |
: 0x48 |
|
Absolute Address |
: 0x348 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Gradient 3 |
RW - - |
0x0000 0000 |
6
|
Description |
: Abscissa 0 |
|
Offset |
: 0x4C |
|
Absolute Address |
: 0x34C |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Abscissa 0 |
RW - - |
0x0000 |
6
|
Description |
: Abscissa 1 |
|
Offset |
: 0x4E |
|
Absolute Address |
: 0x34E |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Abscissa 1 |
RW - - |
0x0000 |
6
|
Description |
: Abscissa 2 |
|
Offset |
: 0x50 |
|
Absolute Address |
: 0x350 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Abscissa 2 |
RW - - |
0x0000 |
6
|
Description |
: Abscissa 3 |
|
Offset |
: 0x52 |
|
Absolute Address |
: 0x352 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Abscissa 3 |
RW - - |
0x0000 |
6
|
Description |
: Ordinate 0 |
|
Offset |
: 0x54 |
|
Absolute Address |
: 0x354 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Ordinate 0 |
RW - - |
0x0000 |
6
|
Description |
: Ordinate 1 |
|
Offset |
: 0x56 |
|
Absolute Address |
: 0x356 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Ordinate 1 |
RW - - |
0x0000 |
6
|
Description |
: Ordinate 2 |
|
Offset |
: 0x58 |
|
Absolute Address |
: 0x358 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Ordinate 2 |
RW - - |
0x0000 |
6
|
Description |
: Ordinate 3 |
|
Offset |
: 0x5A |
|
Absolute Address |
: 0x35A |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Ordinate 3 |
RW - - |
0x0000 |
6
|
Description |
: Gradient 0 |
|
Offset |
: 0x5C |
|
Absolute Address |
: 0x35C |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Gradient 0 |
RW - - |
0x0000 0000 |
6
|
Description |
: Gradient 1 |
|
Offset |
: 0x60 |
|
Absolute Address |
: 0x360 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Gradient 1 |
RW - - |
0x0000 0000 |
6
|
Description |
: Gradient 2 |
|
Offset |
: 0x64 |
|
Absolute Address |
: 0x364 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Gradient 2 |
RW - - |
0x0000 0000 |
6
|
Description |
: Gradient 3 |
|
Offset |
: 0x68 |
|
Absolute Address |
: 0x368 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Gradient 3 |
RW - - |
0x0000 0000 |
6
|
Description |
: Auto wake up controls |
|
Offset |
: 0x6C |
|
Absolute Address |
: 0x36C |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
FRAME_LENGTH_FOR_CONVERGENCE |
|||||||||||||||
|
RW - 0x0316 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
NO_OF_ZONE_TO_WAKEUP |
INTERRUPT_MODE_TO_HOST |
DETECT_BYPASS_ON_EXP_CHANGE |
DETECT_COMPUTE_ZSCORE |
DETECT_COMPARISON_MODE |
DETECT_DECISION_MODE |
LEARNING_MODE |
RESET |
BYPASS |
|||||||
|
RW - 0x01 |
RW - 0x0 |
RW - 0x0 |
RW - 0x1 |
RW - 0x1 |
RW - 0x0 |
RW - 0x0 |
RW - 0x1 |
RW - 0x0 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:16 |
FRAME_LENGTH_FOR_CONVERGENCE |
Frame length of AWU first convergence cycle |
RW - - |
0x0316 |
|
15:11 |
NO_OF_ZONE_TO_WAKEUP |
Number of zones needed to detect movement |
RW - - |
0x01 |
|
10 |
INTERRUPT_MODE_TO_HOST |
0x0 GPIO: GPIO 0x1 I3C_SLAVE_IBI: I3C_SLAVE_IBI |
RW - - |
0x0 |
|
9 |
DETECT_BYPASS_ON_EXP_CHANGE |
Bypass detection when the current exposure is different from the previous one 0x0 FALSE: FALSE 0x1 TRUE: TRUE |
RW - - |
0x0 |
|
8 |
DETECT_COMPUTE_ZSCORE |
Compute Z-scores 0x0 FALSE: FALSE 0x1 TRUE: TRUE |
RW - - |
0x1 |
|
7:6 |
DETECT_COMPARISON_MODE |
0x0 BYPASS: BYPASS 0x1 ZSCORE: ZSCORE |
RW - - |
0x1 |
|
5:4 |
DETECT_DECISION_MODE |
0x0 GLOBAL: GLOBAL |
RW - - |
0x0 |
|
3:2 |
LEARNING_MODE |
Choice of learning algorithm 0x00 TEMPORAL_AVERAGE_LEAKY: TEMPORAL_AVERAGE_LEAKY 0x01 TEMPORAL_AVERAGE_WINDOW: TEMPORAL_AVERAGE_WINDOW |
RW - - |
0x0 |
|
1 |
RESET |
0x0 DISABLE: DISABLE 0x1 ENABLE: ENABLE |
RW - - |
0x1 |
|
0 |
BYPASS |
0x0 DISABLE: DISABLE 0x1 ENABLE: ENABLE |
RW - - |
0x0 |
6
Register: AWU_DETECTION_THRESHOLD
|
Description |
: Auto wake up detection threshold |
|
Offset |
: 0x70 |
|
Absolute Address |
: 0x370 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RW - 0x06 |
RW - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Integer |
RW - - |
0x06 |
|
7:0 |
FRACT |
Fractional |
RW - - |
0x00 |
6
Register: EXPOSURE_USER_MAX_COARSE_INTEGRATION_LINES
|
Description |
: Maximum integration tim |
|
Offset |
: 0x72 |
|
Absolute Address |
: 0x372 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x7FFF |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
User maximum coarse integration [15 bits maximum]. It is mainly used for AWU, convergence, and detection. |
RW - - |
0x7FFF |
6
Register: EXPOSURE_COLDSTART_EXPOSURE_TIME_US_A
|
Description |
: Cold start for the auto exposure instance A |
|
Offset |
: 0x74 |
|
Absolute Address |
: 0x374 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 07D0 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 07D0 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Coarse exposure time in microseconds for the first exposure |
RW - - |
0x0000 07D0 |
6
Register: EXPOSURE_COLDSTART_EXPOSURE_TIME_US_B
|
Description |
: Cold start for the auto exposure instance B |
|
Offset |
: 0x78 |
|
Absolute Address |
: 0x378 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 07D0 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 07D0 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Coarse exposure time in microseconds for the second exposure |
RW - - |
0x0000 07D0 |
6
Register: EXPOSURE_COARSE_INTG_MARGIN
|
Description |
: Margin of the integration time compare to the frame length |
|
Offset |
: 0x7C |
|
Absolute Address |
: 0x37C |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
ADC_10BIT |
|||||||||||||||
|
RW - 0x0039 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
ADC_9BIT |
|||||||||||||||
|
RW - 0x0039 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:16 |
ADC_10BIT |
Coarse integration exposure margin for the 10-bit ADC |
RW - - |
0x0039 |
|
15:0 |
ADC_9BIT |
Coarse integration exposure margin for the 9-bit ADC |
RW - - |
0x0039 |
6
Register: EXPOSURE_MINIMUM_COARSE_LINES
|
Description |
: Minimum integration time |
|
Offset |
: 0x80 |
|
Absolute Address |
: 0x380 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
ADC_10BIT |
|||||||||||||||
|
RW - 0x0004 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
ADC_9BIT |
|||||||||||||||
|
RW - 0x0005 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:16 |
ADC_10BIT |
Minimum exposure in 10-bit mode |
RW - - |
0x0004 |
|
15:0 |
ADC_9BIT |
Minimum exposure in 9-bit mode |
RW - - |
0x0005 |
6
|
Description |
: Auto wake up controls |
|
Offset |
: 0x84 |
|
Absolute Address |
: 0x384 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
|
DDC_BYPASS_DARKAVG |
DUSTER_BYPASS |
HDEFCOR_BYPASS |
|||||||||||
|
RW - 0x0 |
|
RW - 0x1 |
RW - 0x1 |
RW - 0x1 |
|||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
2 |
DDC_BYPASS_DARKAVG |
DARKCAL_BYPASS_DARKAVG 0x0 DISABLE: DISABLE 0x1 ENABLE: ENABLE |
RW - - |
0x1 |
|
1 |
DUSTER_BYPASS |
DUSTER control 0x0 DISABLE: DISABLE 0x1 ENABLE: ENABLE |
RW - - |
0x1 |
|
0 |
HDEFCOR_BYPASS |
HDEFCOR control 0x0 DISABLE: DISABLE 0x1 ENABLE: ENABLE |
RW - - |
0x1 |
6
Register: EXPOSURE_OVER_EXPOSURE_IN_FLICKER_FREE_IN_EV_A
|
Description |
: Allowed excess exposure in flicker free in EV for A |
|
Offset |
: 0x86 |
|
Absolute Address |
: 0x386 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RW - 0x00 |
RW - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Allowed excess exposure in flicker free in EV for A |
RW - - |
0x00 |
|
7:0 |
FRACT |
Allowed excess exposure in flicker free in EV for A |
RW - - |
0x00 |
6
Register: EXPOSURE_OVER_EXPOSURE_IN_FLICKER_FREE_IN_EV_B
|
Description |
: Allowed excess exposure in flicker free in EV for B |
|
Offset |
: 0x88 |
|
Absolute Address |
: 0x388 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RW - 0x00 |
RW - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Allowed excess exposure in flicker free in EV for B |
RW - - |
0x00 |
|
7:0 |
FRACT |
Allowed excess exposure in flicker free in EV for B |
RW - - |
0x00 |
6
Register: EXPOSURE_COMPILATION_PROBLEM_THRESHOLD_RATIO
|
Description |
: Compilation problem threshold ration |
|
Offset |
: 0x8A |
|
Absolute Address |
: 0x38A |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
INTEGER |
FRACT |
|||||||||||||
|
|
RW - 0x1 |
RW - 0x33 |
|||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
9:8 |
INTEGER |
Compilation problem threshold ration (integer part) |
RW - - |
0x1 |
|
7:0 |
FRACT |
Compilation problem threshold ration (fractional part) |
RW - - |
0x33 |
6
|
Description |
: Noise generator configuration |
|
Offset |
: 0xAC |
|
Absolute Address |
: 0x3AC |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
VALUE |
||||||||||||||
|
RW - 0x00 |
RW - 0x7F |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
7:0 |
VALUE |
Noise generator configuration registers |
RW - - |
0x7F |
6
|
Description |
: Defect correction and noise reduction controls |
|
Offset |
: 0xAE |
|
Absolute Address |
: 0x3AE |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
NOISE_CORRECTION |
RING_ENABLE |
GAUSSIAN_MONO5X5_ENABLE |
DYN_ENABLE |
ENABLE |
||||||||||
|
RW - 0x000 |
RW - 0x0 |
RW - 0x1 |
RW - 0x0 |
RW - 0x1 |
RW - 0x1 |
||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:6 |
RESERVED0 |
Reserved |
RW - - |
0x000 |
|
5 |
NOISE_CORRECTION |
Enable/Disable and strength control 0x0 DISABLE: DISABLE 0x1 ENABLE: ENABLE |
RW - - |
0x0 |
|
4 |
RING_ENABLE |
Duster ring correction control 0x0 DISABLE: = disable duster ring correction 0x1 ENABLE: = enable duster ring correction |
RW - - |
0x1 |
|
3 |
GAUSSIAN_MONO5X5_ENABLE |
Gaussian mono5X5 control 0x0 DISABLE: = use 3x3 filter 0x1 ENABLE: = use 5x5 filter |
RW - - |
0x0 |
|
2:1 |
DYN_ENABLE |
Duster mode control 0x0 BYPASS: = disable duster dynamic correction 0x1 AUTO: = duster corrects singlets and couplets 0x2 COUPLET: = duster corrects only couplets |
RW - - |
0x1 |
|
0 |
ENABLE |
Duster mode control 0x0 BYPASS: = fully disable duster 0x1 ENABLE: = enable duster modules |
RW - - |
0x1 |
6
Register: CONTEXT_REPEAT_COUNT_CTX0
|
Description |
: Number of frame to be output from context 0 |
|
Offset |
: 0xDC |
|
Absolute Address |
: 0x3DC |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Number of frames per context |
RW - - |
0x0000 |
6
Register: CONTEXT_REPEAT_COUNT_CTX1
|
Description |
: Number of frame to be output from context 1 |
|
Offset |
: 0xDE |
|
Absolute Address |
: 0x3DE |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Number of frames per context |
RW - - |
0x0000 |
6
Register: CONTEXT_REPEAT_COUNT_CTX2
|
Description |
: Number of frame to be output from context 2 |
|
Offset |
: 0xE0 |
|
Absolute Address |
: 0x3E0 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Number of frames per context |
RW - - |
0x0000 |
6
Register: CONTEXT_REPEAT_COUNT_CTX3
|
Description |
: Number of frame to be output from context 3 |
|
Offset |
: 0xE2 |
|
Absolute Address |
: 0x3E2 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Number of frames per context |
RW - - |
0x0000 |
6
Register: CONTEXT_NEXT_CONTEXT
|
Description |
: Context chaining |
|
Offset |
: 0xE4 |
|
Absolute Address |
: 0x3E4 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
CTX3 |
CTX2 |
CTX1 |
CTX0 |
||||||||||||
|
RW - 0x1 |
RW - 0x1 |
RW - 0x1 |
RW - 0x1 |
||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:12 |
CTX3 |
Next context target, if > 3, stop streaming occurs after a repeat count |
RW - - |
0x1 |
|
11:8 |
CTX2 |
Next context target, if > 3, stop streaming occurs after a repeat count |
RW - - |
0x1 |
|
7:4 |
CTX1 |
Next context target, if > 3, stop streaming occurs after a repeat count |
RW - - |
0x1 |
|
3:0 |
CTX0 |
Next context target, if > 3, stop streaming occurs after a repeat count |
RW - - |
0x1 |
6
Register: VT_SUB_DIGITAL_OFFSET
|
Description |
: Offset for the subtraction |
|
Offset |
: 0xE6 |
|
Absolute Address |
: 0x3E6 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
DIGITAL_OFFSET |
||||||||||||||
|
|
RW - 0x200 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
9:0 |
DIGITAL_OFFSET |
Offset for VT-SUB which is 512: power(2, bitwidth-1) |
RW - - |
0x200 |
6
|
Description |
: Delay between 2 frames in subtraction mode |
|
Offset |
: 0xE8 |
|
Absolute Address |
: 0x3E8 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
RESERVED0 |
VT_SUB_WAIT_PIXELS |
||||||||||||||
|
RW - 0x0 |
RW - 0x0000 |
||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VT_SUB_WAIT_LINES |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:29 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
28:16 |
VT_SUB_WAIT_PIXELS |
Delay in pixels (13 bits) between two integrations in VT subtraction mode |
RW - - |
0x0000 |
|
15:0 |
VT_SUB_WAIT_LINES |
Delay in lines between two integrations in VT subtraction mode |
RW - - |
0x0000 |
6
Block: STREAM_DYNAMICS
|
Description |
: Dynamic setting releated to streaming from Wolfy sensor |
3
|
Description |
: Hold the application of the dynamic parameters |
|
Offset |
: 0x1 |
|
Absolute Address |
: 0x481 |
|
Addressing Mode |
: 16-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
HOLD |
||||||
|
|
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
0 |
HOLD |
Hold the application of dynamic parameters |
RW - - |
0x0 |
6
Register: EXPOSURE_COMPILER_CONTROL_A
|
Description |
: Controls of the auto exposure A |
|
Offset |
: 0x2 |
|
Absolute Address |
: 0x482 |
|
Addressing Mode |
: 16-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
FLICKER_FREQUENCY |
MODE |
|||||||||||||
|
RW - 0x0000 |
RW - 0x0 |
RW - 0x0 |
|||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:2 |
RESERVED0 |
Reserved |
RW - - |
0x0000 |
|
1 |
FLICKER_FREQUENCY |
0x0 DEF_50Hz: DEF_50Hz 0x1 DEF_60Hz: DEF_60Hz |
RW - - |
0x0 |
|
0 |
MODE |
0x0 MINIMUM_GAIN: MINIMUM_GAIN 0x1 FLICKER_FREE: FLICKER_FREE |
RW - - |
0x0 |
6
Register: EXPOSURE_COMPENSATION_A
|
Description |
: Exposure compensation for the auto exposure A |
|
Offset |
: 0x4 |
|
Absolute Address |
: 0x484 |
|
Addressing Mode |
: 16-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RW - 0x00 |
RW - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Change the target exposure in stops by increasing or decreasing the integer part of this value |
RW - - |
0x00 |
|
7:0 |
FRACT |
Change the target exposure in stops by increasing or decreasing the fractional part of this value |
RW - - |
0x00 |
6
Register: EXPOSURE_TARGET_PERCENTAGE_A
|
Description |
: Target of the auto exposure A |
|
Offset |
: 0x6 |
|
Absolute Address |
: 0x486 |
|
Addressing Mode |
: 16-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RW - 0x1B |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
This is the target in percent which the exposure algorithm tries to achieve in integers |
RW - - |
0x1B |
6
Register: EXPOSURE_STEP_PROPORTION_A
|
Description |
: Maximum step of the auto exposure A |
|
Offset |
: 0x8 |
|
Absolute Address |
: 0x488 |
|
Addressing Mode |
: 16-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RW - 0x00 |
RW - 0x80 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Fixed point step proportion (8.8) |
RW - - |
0x00 |
|
7:0 |
FRACT |
Fixed point step proportion (8.8) |
RW - - |
0x80 |
6
Register: EXPOSURE_LEAK_PROPORTION_A
|
Description |
: Leak proportion of the auto exposure A |
|
Offset |
: 0xA |
|
Absolute Address |
: 0x48A |
|
Addressing Mode |
: 16-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RW - 0x0 |
RW - 0x1F40 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15 |
INTEGER |
Fixed point step proportion (1.15) |
RW - - |
0x0 |
|
14:0 |
FRACT |
Fixed point step proportion (1.15) |
RW - - |
0x1F40 |
6
Register: EXPOSURE_COMPILER_CONTROL_B
|
Description |
: Controls of the auto exposure B |
|
Offset |
: 0xC |
|
Absolute Address |
: 0x48C |
|
Addressing Mode |
: 16-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
FLICKER_FREQUENCY |
MODE |
|||||||||||||
|
RW - 0x0000 |
RW - 0x0 |
RW - 0x0 |
|||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:2 |
RESERVED0 |
Reserved |
RW - - |
0x0000 |
|
1 |
FLICKER_FREQUENCY |
0x0 DEF_50Hz: DEF_50Hz 0x1 DEF_60Hz: DEF_60Hz |
RW - - |
0x0 |
|
0 |
MODE |
0x0 MINIMUM_GAIN: MINIMUM_GAIN 0x1 FLICKER_FREE: FLICKER_FREE |
RW - - |
0x0 |
6
Register: EXPOSURE_COMPENSATION_B
|
Description |
: Exposure compensation for the auto exposure B |
|
Offset |
: 0xE |
|
Absolute Address |
: 0x48E |
|
Addressing Mode |
: 16-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RW - 0x00 |
RW - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Change the target exposure in stops by increasing or decreasing this value |
RW - - |
0x00 |
|
7:0 |
FRACT |
Change the target exposure in stops by increasing or decreasing this value |
RW - - |
0x00 |
6
Register: EXPOSURE_TARGET_PERCENTAGE_B
|
Description |
: Target of the auto exposure B |
|
Offset |
: 0x10 |
|
Absolute Address |
: 0x490 |
|
Addressing Mode |
: 16-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RW - 0x1B |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
This is the target in percent which the exposure algorithm tries to achieve in integers |
RW - - |
0x1B |
6
Register: EXPOSURE_STEP_PROPORTION_B
|
Description |
: Maximum step of the auto exposure B |
|
Offset |
: 0x12 |
|
Absolute Address |
: 0x492 |
|
Addressing Mode |
: 16-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RW - 0x00 |
RW - 0x80 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Fixed point step proportion (8.8) |
RW - - |
0x00 |
|
7:0 |
FRACT |
Fixed point step proportion (8.8) |
RW - - |
0x80 |
6
Register: EXPOSURE_LEAK_PROPORTION_B
|
Description |
: Leak proportion of the auto exposure B |
|
Offset |
: 0x14 |
|
Absolute Address |
: 0x494 |
|
Addressing Mode |
: 16-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RW - 0x0 |
RW - 0x1F40 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15 |
INTEGER |
Fixed point step proportion (1.15) |
RW - - |
0x0 |
|
14:0 |
FRACT |
Fixed point step proportion (1.15) |
RW - - |
0x1F40 |
6
|
Description |
: Minimum exposure step to change exposure |
|
Offset |
: 0x1C |
|
Absolute Address |
: 0x49C |
|
Addressing Mode |
: 16-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RW - 0x00 |
RW - 0x02 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Minimum step of integer part |
RW - - |
0x00 |
|
7:0 |
FRACT |
Minimum step of fractional part |
RW - - |
0x02 |
6
|
Description |
: Maximum exposure step |
|
Offset |
: 0x1E |
|
Absolute Address |
: 0x49E |
|
Addressing Mode |
: 16-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RW - 0x04 |
RW - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Maximum step of integer part |
RW - - |
0x04 |
|
7:0 |
FRACT |
Maximum step of fractional part |
RW - - |
0x00 |
6
Register: EXPOSURE_FLICKER_TOLERANCE_PERCENT
|
Description |
: Tolerance of the auto exposure when aligned to the flicker frequency |
|
Offset |
: 0x20 |
|
Absolute Address |
: 0x4A0 |
|
Addressing Mode |
: 16-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RW - 0x05 |
RW - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Tolerance percent of integer part |
RW - - |
0x05 |
|
7:0 |
FRACT |
Tolerance percent of fractional part |
RW - - |
0x00 |
6
Block: STREAM_CTX0
|
Description |
: Context0 group elements |
3
|
Description |
: Exposure mode control |
|
Offset |
: 0x0 |
|
Absolute Address |
: 0x500 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
MODE |
||||||
|
RW - 0x00 |
RW - 0x2 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:3 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
2:0 |
MODE |
Exposure mode control 0x0 AUTO_MEAN: = automatic mode 0x1 FREEZE: = freeze AE with current settings 0x2 MANUAL: = manual setting mode 0x4 BYPASS: BYPASS |
RW - - |
0x2 |
6
Register: EXPOSURE_MANUAL_ANALOG_GAIN
|
Description |
: Manual analog gain |
|
Offset |
: 0x1 |
|
Absolute Address |
: 0x501 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
VALUE |
||||||
|
RW - 0x0 |
RW - 0x00 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:5 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
4:0 |
VALUE |
0x00 AnalogGain_AGAIN_1: AnalogGain_AGAIN_1 0x01 AnalogGain_AGAIN_1_03: AnalogGain_AGAIN_1_03 0x02 AnalogGain_AGAIN_1_07: AnalogGain_AGAIN_1_07 0x03 AnalogGain_AGAIN_1_1: AnalogGain_AGAIN_1_1 0x04 AnalogGain_AGAIN_1_14: AnalogGain_AGAIN_1_14 0x05 AnalogGain_AGAIN_1_19: AnalogGain_AGAIN_1_19 0x06 AnalogGain_AGAIN_1_23: AnalogGain_AGAIN_1_23 0x07 AnalogGain_AGAIN_1_28: AnalogGain_AGAIN_1_28 0x08 AnalogGain_AGAIN_1_33: AnalogGain_AGAIN_1_33 0x09 AnalogGain_AGAIN_1_39: AnalogGain_AGAIN_1_39 0x0A AnalogGain_AGAIN_1_45: AnalogGain_AGAIN_1_45 0x0B AnalogGain_AGAIN_1_52: AnalogGain_AGAIN_1_52 0x0C AnalogGain_AGAIN_1_6: AnalogGain_AGAIN_1_6 0x0D AnalogGain_AGAIN_1_68: AnalogGain_AGAIN_1_68 0x0E AnalogGain_AGAIN_1_78: AnalogGain_AGAIN_1_78 0x0F AnalogGain_AGAIN_1_88: AnalogGain_AGAIN_1_88 0x10 AnalogGain_AGAIN_2: AnalogGain_AGAIN_2 0x11 AnalogGain_AGAIN_2_13: AnalogGain_AGAIN_2_13 0x12 AnalogGain_AGAIN_2_29: AnalogGain_AGAIN_2_29 0x13 AnalogGain_AGAIN_2_46: AnalogGain_AGAIN_2_46 0x14 AnalogGain_AGAIN_2_67: AnalogGain_AGAIN_2_67 0x15 AnalogGain_AGAIN_2_91: AnalogGain_AGAIN_2_91 0x16 AnalogGain_AGAIN_3_2: AnalogGain_AGAIN_3_2 0x17 AnalogGain_AGAIN_3_56: AnalogGain_AGAIN_3_56 0x18 AnalogGain_AGAIN_4: AnalogGain_AGAIN_4 0x19 AnalogGain_AGAIN_4_5714: AnalogGain_AGAIN_4_5714 0x1A AnalogGain_AGAIN_5_3333: AnalogGain_AGAIN_5_3333 0x1B AnalogGain_AGAIN_6_4: AnalogGain_AGAIN_6_4 0x1C AnalogGain_AGAIN_8_0: AnalogGain_AGAIN_8_0 |
RW - - |
0x00 |
6
Register: EXPOSURE_MANUAL_COARSE_EXPOSURE_LINES_A
|
Description |
: Manual coarse exposure |
|
Offset |
: 0x2 |
|
Absolute Address |
: 0x502 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0032 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Coarse exposure time in lines |
RW - - |
0x0032 |
6
Register: EXPOSURE_MANUAL_DIGITAL_GAIN_CH0
|
Description |
: Manual digital gain |
|
Offset |
: 0x4 |
|
Absolute Address |
: 0x504 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RW - 0x01 |
RW - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Digital gain (integer part) for channel 0 in manual mode |
RW - - |
0x01 |
|
7:0 |
FRACT |
Digital gain (fractional part) for channel 0 in manual mode |
RW - - |
0x00 |
6
|
Description |
: Length of the frame |
|
Offset |
: 0xC |
|
Absolute Address |
: 0x50C |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0316 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0316 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Length of the frame (including blanking in lines) |
RW - - |
0x0000 0316 |
6
|
Description |
: Y start for image output |
|
Offset |
: 0x10 |
|
Absolute Address |
: 0x510 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Y start for image output |
RW - - |
0x0000 |
6
|
Description |
: Y height for image output |
|
Offset |
: 0x12 |
|
Absolute Address |
: 0x512 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x02C0 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Y height for image output |
RW - - |
0x02C0 |
6
|
Description |
: X start for image output |
|
Offset |
: 0x14 |
|
Absolute Address |
: 0x514 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
X start for image output |
RW - - |
0x0000 |
6
|
Description |
: X wIdth for image output |
|
Offset |
: 0x16 |
|
Absolute Address |
: 0x516 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0324 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
X width for image output |
RW - - |
0x0324 |
6
Register: EXPOSURE_STATS_ACTIVE_ZONE
|
Description |
: Active zones for the auto exposure statistique computation |
|
Offset |
: 0x18 |
|
Absolute Address |
: 0x518 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0xFFFF |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Active zones for the auto exposure statistique computation |
RW - - |
0xFFFF |
6
Register: EXPOSURE_STATS_ACTIVE_ZONE_WEIGHT
|
Description |
: Statistics zone weight |
|
Offset |
: 0x1A |
|
Absolute Address |
: 0x51A |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RW - 0x64 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Statistics zone weight |
RW - - |
0x64 |
6
|
Description |
: Marker used by host |
|
Offset |
: 0x1B |
|
Absolute Address |
: 0x51B |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Marker used by host |
RW - - |
0x00 |
6
|
Description |
: Control of the GPIO 0 |
|
Offset |
: 0x1D |
|
Absolute Address |
: 0x51D |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
Polarity |
VALUE |
Mode |
||||
|
RW - 0x0 |
RW - 0x0 |
RW - 0x0 |
RW - 0x1 |
||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:6 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
5 |
Polarity |
Polarity value 0x0 NO_INVERSION: NO_INVERSION 0x1 INVERTED: INVERTED |
RW - - |
0x0 |
|
4 |
VALUE |
GPIO value 0x0 GPIO_LOW: GPIO_LOW 0x1 GPIO_HIGH: GPIO_HIGH |
RW - - |
0x0 |
|
3:0 |
Mode |
GPIO mode 0x0 FSYNC_OUT: FSYNC_OUT 0x1 GPIO_IN: GPIO_IN 0x2 STROBE: STROBE 0x3 PWM_STROBE: PWM_STROBE 0x4 PWM: PWM 0x5 GPIO_OUT: GPIO_OUT 0x6 VSYNC_OUT_MODE0: VSYNC_OUT_MODE0 0x7 VSYNC_OUT_MODE1: VSYNC_OUT_MODE1 0x8 VSYNC_OUT_MODE2: VSYNC_OUT_MODE2 0x9 EVENT_TRACKER: EVENT_TRACKER 0xA VT_SLAVE_MODE: VT_SLAVE_MODE 0xC IMAGE_READOUT: IMAGE_READOUT 0xD AWU_DETECTION: AWU_DETECTION |
RW - - |
0x1 |
6
|
Description |
: Control of the GPIO 1 |
|
Offset |
: 0x1E |
|
Absolute Address |
: 0x51E |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
Polarity |
VALUE |
Mode |
||||
|
RW - 0x0 |
RW - 0x0 |
RW - 0x0 |
RW - 0x2 |
||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:6 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
5 |
Polarity |
Polarity value 0x0 NO_INVERSION: NO_INVERSION 0x1 INVERTED: INVERTED |
RW - - |
0x0 |
|
4 |
VALUE |
GPIO value 0x0 GPIO_LOW: GPIO_LOW 0x1 GPIO_HIGH: GPIO_HIGH |
RW - - |
0x0 |
|
3:0 |
Mode |
GPIO mode 0x0 FSYNC_OUT: FSYNC_OUT 0x1 GPIO_IN: GPIO_IN 0x2 STROBE: STROBE 0x3 PWM_STROBE: PWM_STROBE 0x4 PWM: PWM 0x5 GPIO_OUT: GPIO_OUT 0x6 VSYNC_OUT_MODE0: VSYNC_OUT_MODE0 0x7 VSYNC_OUT_MODE1: VSYNC_OUT_MODE1 0x8 VSYNC_OUT_MODE2: VSYNC_OUT_MODE2 0x9 EVENT_TRACKER: EVENT_TRACKER 0xC IMAGE_READOUT: IMAGE_READOUT 0xD AWU_DETECTION: AWU_DETECTION |
RW - - |
0x2 |
6
|
Description |
: Control of the GPIO 2 |
|
Offset |
: 0x1F |
|
Absolute Address |
: 0x51F |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
Polarity |
VALUE |
Mode |
||||
|
RW - 0x0 |
RW - 0x0 |
RW - 0x0 |
RW - 0x6 |
||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:6 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
5 |
Polarity |
Polarity value 0x0 NO_INVERSION: NO_INVERSION 0x1 INVERTED: INVERTED |
RW - - |
0x0 |
|
4 |
VALUE |
GPIO value 0x0 GPIO_LOW: GPIO_LOW 0x1 GPIO_HIGH: GPIO_HIGH |
RW - - |
0x0 |
|
3:0 |
Mode |
GPIO mode 0x0 FSYNC_OUT: FSYNC_OUT 0x1 GPIO_IN: GPIO_IN 0x2 STROBE: STROBE 0x3 PWM_STROBE: PWM_STROBE 0x4 PWM: PWM 0x5 GPIO_OUT: GPIO_OUT 0x6 VSYNC_OUT_MODE0: VSYNC_OUT_MODE0 0x7 VSYNC_OUT_MODE1: VSYNC_OUT_MODE1 0x8 VSYNC_OUT_MODE2: VSYNC_OUT_MODE2 0x9 EVENT_TRACKER: EVENT_TRACKER 0xC IMAGE_READOUT: IMAGE_READOUT 0xD AWU_DETECTION: AWU_DETECTION |
RW - - |
0x6 |
6
|
Description |
: Control of the GPIO 3 |
|
Offset |
: 0x20 |
|
Absolute Address |
: 0x520 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
Polarity |
VALUE |
Mode |
||||
|
RW - 0x0 |
RW - 0x0 |
RW - 0x0 |
RW - 0x2 |
||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:6 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
5 |
Polarity |
Polarity value 0x0 NO_INVERSION: NO_INVERSION 0x1 INVERTED: INVERTED |
RW - - |
0x0 |
|
4 |
VALUE |
GPIO value 0x0 GPIO_LOW: GPIO_LOW 0x1 GPIO_HIGH: GPIO_HIGH |
RW - - |
0x0 |
|
3:0 |
Mode |
GPIO mode 0x0 FSYNC_OUT: FSYNC_OUT 0x1 GPIO_IN: GPIO_IN 0x2 STROBE: STROBE 0x3 PWM_STROBE: PWM_STROBE 0x4 PWM: PWM 0x5 GPIO_OUT: GPIO_OUT 0x6 VSYNC_OUT_MODE0: VSYNC_OUT_MODE0 0x7 VSYNC_OUT_MODE1: VSYNC_OUT_MODE1 0x8 VSYNC_OUT_MODE2: VSYNC_OUT_MODE2 0x9 EVENT_TRACKER: EVENT_TRACKER 0xC IMAGE_READOUT: IMAGE_READOUT 0xD AWU_DETECTION: AWU_DETECTION |
RW - - |
0x2 |
6
|
Description |
: Capabilty to shift the start of the VSYNC |
|
Offset |
: 0x21 |
|
Absolute Address |
: 0x521 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
DELAY_L |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
DELAY_L |
Signed value of the delay to apply in lines |
RW - - |
0x00 |
6
|
Description |
: Capabilty to shift the end of the VSYNC |
|
Offset |
: 0x22 |
|
Absolute Address |
: 0x522 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
DELAY_L |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
DELAY_L |
Signed value of the delay to apply in lines |
RW - - |
0x00 |
6
|
Description |
: Capabilty to shift the start of the STROBE |
|
Offset |
: 0x23 |
|
Absolute Address |
: 0x523 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
DELAY_L |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
DELAY_L |
Signed value of the delay to apply in lines |
RW - - |
0x00 |
6
|
Description |
: Capabilty to shift the end of the STROBE |
|
Offset |
: 0x24 |
|
Absolute Address |
: 0x524 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
DELAY_L |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
DELAY_L |
Signed value of the delay to apply in lines |
RW - - |
0x00 |
6
|
Description |
: Pedestal to be applied |
|
Offset |
: 0x26 |
|
Absolute Address |
: 0x526 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0008 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
DarkCal pedestal |
RW - - |
0x0008 |
6
|
Description |
: Controls of the PWM |
|
Offset |
: 0x28 |
|
Absolute Address |
: 0x528 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
CLkDivisor |
|||||||||||||||
|
RW - 0x0064 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
DutyCycle |
||||||||||||||
|
|
RW - 0x7 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:16 |
CLkDivisor |
Number of pulses to send out |
RW - - |
0x0064 |
|
3:0 |
DutyCycle |
Duty cycle in percent |
RW - - |
0x7 |
6
|
Description |
: Control of the PWL |
|
Offset |
: 0x2C |
|
Absolute Address |
: 0x52C |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
LUT_SEL |
||||||
|
RW - 0x00 |
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:2 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
1:0 |
LUT_SEL |
Piecewise linear transformation look up table 0x0 DEFAULT0: DEFAULT0 0x1 DEFAULT1: DEFAULT1 0x2 USER0: USER0 0x3 USER1: USER1 |
RW - - |
0x0 |
6
|
Description |
: Instance of exposure to be used in this context |
|
Offset |
: 0x2D |
|
Absolute Address |
: 0x52D |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Instance 0x0 INSTANCE_A: INSTANCE_A 0x1 INSTANCE_B: INSTANCE_B |
RW - - |
0x00 |
6
|
Description |
: Decimation control |
|
Offset |
: 0x2E |
|
Absolute Address |
: 0x52E |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
CFG |
||||||
|
RW - 0x00 |
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:3 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
2:0 |
CFG |
Streaming readout mode control 0x00 NORMAL: = normal streaming 0x01 DBIN_X2: = digital binning x2 0x02 DBIN_X4: = digital binning x4 0x03 SSAMP_X2: = subsampling x2 0x04 SSAMP_X4: = subsampling x4 0x05 SSAMP_X8: = subsampling x8 0x06 XYBINNING_X2: = XY binning x2 |
RW - - |
0x0 |
6
Register: EXPOSURE_MANUAL_COARSE_EXPOSURE_LINES_B
|
Description |
: Manual exposure for the second exposure |
|
Offset |
: 0x30 |
|
Absolute Address |
: 0x530 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0032 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Manual exposure for visible medium |
RW - - |
0x0032 |
6
Register: EXPOSURE_MANUAL_COARSE_EXPOSURE_LINES_C
|
Description |
: Manual exposure for the third exposure |
|
Offset |
: 0x32 |
|
Absolute Address |
: 0x532 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0032 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Manual exposure for visible short |
RW - - |
0x0032 |
6
|
Description |
: Subtraction control |
|
Offset |
: 0x36 |
|
Absolute Address |
: 0x536 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
MODE |
||||||
|
RW - 0x00 |
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:1 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
0 |
MODE |
Mode 0x0 MULTI_EXPO: MULTI_EXPO 0x1 VT_SUB: VT_SUB |
RW - - |
0x0 |
6
|
Description |
: Control to mask frames |
|
Offset |
: 0x37 |
|
Absolute Address |
: 0x537 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
MASK |
||||||
|
RW - 0x00 |
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:1 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
0 |
MASK |
Enable/Disable 0x0 DISABLE: DISABLE 0x1 ENABLE: ENABLE |
RW - - |
0x0 |
6
Block: STREAM_CTX1
|
Description |
: Context1 group elements |
3
|
Description |
: Exposure mode control |
|
Offset |
: 0x0 |
|
Absolute Address |
: 0x550 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
MODE |
||||||
|
RW - 0x00 |
RW - 0x2 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:3 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
2:0 |
MODE |
Exposure mode control 0x0 AUTO_MEAN: = automatic mode 0x1 FREEZE: = freeze AE with current settings 0x2 MANUAL: = manual setting mode 0x4 BYPASS: BYPASS |
RW - - |
0x2 |
6
Register: EXPOSURE_MANUAL_ANALOG_GAIN
|
Description |
: Manual analog gain |
|
Offset |
: 0x1 |
|
Absolute Address |
: 0x551 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
VALUE |
||||||
|
RW - 0x0 |
RW - 0x00 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:5 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
4:0 |
VALUE |
0x00 AnalogGain_AGAIN_1: AnalogGain_AGAIN_1 0x01 AnalogGain_AGAIN_1_03: AnalogGain_AGAIN_1_03 0x02 AnalogGain_AGAIN_1_07: AnalogGain_AGAIN_1_07 0x03 AnalogGain_AGAIN_1_1: AnalogGain_AGAIN_1_1 0x04 AnalogGain_AGAIN_1_14: AnalogGain_AGAIN_1_14 0x05 AnalogGain_AGAIN_1_19: AnalogGain_AGAIN_1_19 0x06 AnalogGain_AGAIN_1_23: AnalogGain_AGAIN_1_23 0x07 AnalogGain_AGAIN_1_28: AnalogGain_AGAIN_1_28 0x08 AnalogGain_AGAIN_1_33: AnalogGain_AGAIN_1_33 0x09 AnalogGain_AGAIN_1_39: AnalogGain_AGAIN_1_39 0x0A AnalogGain_AGAIN_1_45: AnalogGain_AGAIN_1_45 0x0B AnalogGain_AGAIN_1_52: AnalogGain_AGAIN_1_52 0x0C AnalogGain_AGAIN_1_6: AnalogGain_AGAIN_1_6 0x0D AnalogGain_AGAIN_1_68: AnalogGain_AGAIN_1_68 0x0E AnalogGain_AGAIN_1_78: AnalogGain_AGAIN_1_78 0x0F AnalogGain_AGAIN_1_88: AnalogGain_AGAIN_1_88 0x10 AnalogGain_AGAIN_2: AnalogGain_AGAIN_2 0x11 AnalogGain_AGAIN_2_13: AnalogGain_AGAIN_2_13 0x12 AnalogGain_AGAIN_2_29: AnalogGain_AGAIN_2_29 0x13 AnalogGain_AGAIN_2_46: AnalogGain_AGAIN_2_46 0x14 AnalogGain_AGAIN_2_67: AnalogGain_AGAIN_2_67 0x15 AnalogGain_AGAIN_2_91: AnalogGain_AGAIN_2_91 0x16 AnalogGain_AGAIN_3_2: AnalogGain_AGAIN_3_2 0x17 AnalogGain_AGAIN_3_56: AnalogGain_AGAIN_3_56 0x18 AnalogGain_AGAIN_4: AnalogGain_AGAIN_4 0x19 AnalogGain_AGAIN_4_5714: AnalogGain_AGAIN_4_5714 0x1A AnalogGain_AGAIN_5_3333: AnalogGain_AGAIN_5_3333 0x1B AnalogGain_AGAIN_6_4: AnalogGain_AGAIN_6_4 0x1C AnalogGain_AGAIN_8_0: AnalogGain_AGAIN_8_0 |
RW - - |
0x00 |
6
Register: EXPOSURE_MANUAL_COARSE_EXPOSURE_LINES_A
|
Description |
: Manual coarse exposure |
|
Offset |
: 0x2 |
|
Absolute Address |
: 0x552 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0032 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Coarse exposure time in lines |
RW - - |
0x0032 |
6
Register: EXPOSURE_MANUAL_DIGITAL_GAIN_CH0
|
Description |
: Manual digital gain |
|
Offset |
: 0x4 |
|
Absolute Address |
: 0x554 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RW - 0x01 |
RW - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Digital gain (integer part) for channel 0 in manual mode |
RW - - |
0x01 |
|
7:0 |
FRACT |
Digital gain (fractional part) for channel 0 in manual mode |
RW - - |
0x00 |
6
|
Description |
: Length of the frame |
|
Offset |
: 0xC |
|
Absolute Address |
: 0x55C |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0316 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0316 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Length of the frame (including blanking in lines) |
RW - - |
0x0000 0316 |
6
|
Description |
: Y start for image output |
|
Offset |
: 0x10 |
|
Absolute Address |
: 0x560 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Y start for image output |
RW - - |
0x0000 |
6
|
Description |
: Y height for image output |
|
Offset |
: 0x12 |
|
Absolute Address |
: 0x562 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x02C0 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Y height for image output |
RW - - |
0x02C0 |
6
|
Description |
: X start for image output |
|
Offset |
: 0x14 |
|
Absolute Address |
: 0x564 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
X start for image output |
RW - - |
0x0000 |
6
|
Description |
: X wIdth for image output |
|
Offset |
: 0x16 |
|
Absolute Address |
: 0x566 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0324 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
X width for image output |
RW - - |
0x0324 |
6
Register: EXPOSURE_STATS_ACTIVE_ZONE
|
Description |
: Active zones for the auto exposure statistique computation |
|
Offset |
: 0x18 |
|
Absolute Address |
: 0x568 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0xFFFF |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Active zones for the auto exposure statistique computation |
RW - - |
0xFFFF |
6
Register: EXPOSURE_STATS_ACTIVE_ZONE_WEIGHT
|
Description |
: Statistics zone weight |
|
Offset |
: 0x1A |
|
Absolute Address |
: 0x56A |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RW - 0x64 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Statistics zone weight |
RW - - |
0x64 |
6
|
Description |
: Marker used by host |
|
Offset |
: 0x1B |
|
Absolute Address |
: 0x56B |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Marker used by host |
RW - - |
0x00 |
6
|
Description |
: Control of the GPIO 0 |
|
Offset |
: 0x1D |
|
Absolute Address |
: 0x56D |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
Polarity |
VALUE |
Mode |
||||
|
RW - 0x0 |
RW - 0x0 |
RW - 0x0 |
RW - 0x1 |
||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:6 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
5 |
Polarity |
Polarity value 0x0 NO_INVERSION: NO_INVERSION 0x1 INVERTED: INVERTED |
RW - - |
0x0 |
|
4 |
VALUE |
GPIO value 0x0 GPIO_LOW: GPIO_LOW 0x1 GPIO_HIGH: GPIO_HIGH |
RW - - |
0x0 |
|
3:0 |
Mode |
GPIO mode 0x0 FSYNC_OUT: FSYNC_OUT 0x1 GPIO_IN: GPIO_IN 0x2 STROBE: STROBE 0x3 PWM_STROBE: PWM_STROBE 0x4 PWM: PWM 0x5 GPIO_OUT: GPIO_OUT 0x6 VSYNC_OUT_MODE0: VSYNC_OUT_MODE0 0x7 VSYNC_OUT_MODE1: VSYNC_OUT_MODE1 0x8 VSYNC_OUT_MODE2: VSYNC_OUT_MODE2 0x9 EVENT_TRACKER: EVENT_TRACKER 0xA VT_SLAVE_MODE: VT_SLAVE_MODE 0xC IMAGE_READOUT: IMAGE_READOUT 0xD AWU_DETECTION: AWU_DETECTION |
RW - - |
0x1 |
6
|
Description |
: Control of the GPIO 1 |
|
Offset |
: 0x1E |
|
Absolute Address |
: 0x56E |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
Polarity |
VALUE |
Mode |
||||
|
RW - 0x0 |
RW - 0x0 |
RW - 0x0 |
RW - 0x2 |
||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:6 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
5 |
Polarity |
Polarity value 0x0 NO_INVERSION: NO_INVERSION 0x1 INVERTED: INVERTED |
RW - - |
0x0 |
|
4 |
VALUE |
GPIO value 0x0 GPIO_LOW: GPIO_LOW 0x1 GPIO_HIGH: GPIO_HIGH |
RW - - |
0x0 |
|
3:0 |
Mode |
GPIO mode 0x0 FSYNC_OUT: FSYNC_OUT 0x1 GPIO_IN: GPIO_IN 0x2 STROBE: STROBE 0x3 PWM_STROBE: PWM_STROBE 0x4 PWM: PWM 0x5 GPIO_OUT: GPIO_OUT 0x6 VSYNC_OUT_MODE0: VSYNC_OUT_MODE0 0x7 VSYNC_OUT_MODE1: VSYNC_OUT_MODE1 0x8 VSYNC_OUT_MODE2: VSYNC_OUT_MODE2 0x9 EVENT_TRACKER: EVENT_TRACKER 0xC IMAGE_READOUT: IMAGE_READOUT 0xD AWU_DETECTION: AWU_DETECTION |
RW - - |
0x2 |
6
|
Description |
: Control of the GPIO 2 |
|
Offset |
: 0x1F |
|
Absolute Address |
: 0x56F |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
Polarity |
VALUE |
Mode |
||||
|
RW - 0x0 |
RW - 0x0 |
RW - 0x0 |
RW - 0x6 |
||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:6 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
5 |
Polarity |
Polarity value 0x0 NO_INVERSION: NO_INVERSION 0x1 INVERTED: INVERTED |
RW - - |
0x0 |
|
4 |
VALUE |
GPIO value 0x0 GPIO_LOW: GPIO_LOW 0x1 GPIO_HIGH: GPIO_HIGH |
RW - - |
0x0 |
|
3:0 |
Mode |
GPIO mode 0x0 FSYNC_OUT: FSYNC_OUT 0x1 GPIO_IN: GPIO_IN 0x2 STROBE: STROBE 0x3 PWM_STROBE: PWM_STROBE 0x4 PWM: PWM 0x5 GPIO_OUT: GPIO_OUT 0x6 VSYNC_OUT_MODE0: VSYNC_OUT_MODE0 0x7 VSYNC_OUT_MODE1: VSYNC_OUT_MODE1 0x8 VSYNC_OUT_MODE2: VSYNC_OUT_MODE2 0x9 EVENT_TRACKER: EVENT_TRACKER 0xC IMAGE_READOUT: IMAGE_READOUT 0xD AWU_DETECTION: AWU_DETECTION |
RW - - |
0x6 |
6
|
Description |
: Control of the GPIO 3 |
|
Offset |
: 0x20 |
|
Absolute Address |
: 0x570 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
Polarity |
VALUE |
Mode |
||||
|
RW - 0x0 |
RW - 0x0 |
RW - 0x0 |
RW - 0x2 |
||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:6 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
5 |
Polarity |
Polarity value 0x0 NO_INVERSION: NO_INVERSION 0x1 INVERTED: INVERTED |
RW - - |
0x0 |
|
4 |
VALUE |
GPIO value 0x0 GPIO_LOW: GPIO_LOW 0x1 GPIO_HIGH: GPIO_HIGH |
RW - - |
0x0 |
|
3:0 |
Mode |
GPIO mode 0x0 FSYNC_OUT: FSYNC_OUT 0x1 GPIO_IN: GPIO_IN 0x2 STROBE: STROBE 0x3 PWM_STROBE: PWM_STROBE 0x4 PWM: PWM 0x5 GPIO_OUT: GPIO_OUT 0x6 VSYNC_OUT_MODE0: VSYNC_OUT_MODE0 0x7 VSYNC_OUT_MODE1: VSYNC_OUT_MODE1 0x8 VSYNC_OUT_MODE2: VSYNC_OUT_MODE2 0x9 EVENT_TRACKER: EVENT_TRACKER 0xC IMAGE_READOUT: IMAGE_READOUT 0xD AWU_DETECTION: AWU_DETECTION |
RW - - |
0x2 |
6
|
Description |
: Capabilty to shift the start of the VSYNC |
|
Offset |
: 0x21 |
|
Absolute Address |
: 0x571 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
DELAY_L |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
DELAY_L |
Signed value of the delay to apply in lines |
RW - - |
0x00 |
6
|
Description |
: Capabilty to shift the end of the VSYNC |
|
Offset |
: 0x22 |
|
Absolute Address |
: 0x572 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
DELAY_L |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
DELAY_L |
Signed value of the delay to apply in lines |
RW - - |
0x00 |
6
|
Description |
: Capabilty to shift the start of the STROBE |
|
Offset |
: 0x23 |
|
Absolute Address |
: 0x573 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
DELAY_L |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
DELAY_L |
Signed value of the delay to apply in lines |
RW - - |
0x00 |
6
|
Description |
: Capabilty to shift the end of the STROBE |
|
Offset |
: 0x24 |
|
Absolute Address |
: 0x574 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
DELAY_L |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
DELAY_L |
Signed value of the delay to apply in lines |
RW - - |
0x00 |
6
|
Description |
: Pedestal to be applied |
|
Offset |
: 0x26 |
|
Absolute Address |
: 0x576 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0008 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
DarkCal pedestal |
RW - - |
0x0008 |
6
|
Description |
: Controls of the PWM |
|
Offset |
: 0x28 |
|
Absolute Address |
: 0x578 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
CLkDivisor |
|||||||||||||||
|
RW - 0x0064 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
DutyCycle |
||||||||||||||
|
|
RW - 0x7 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:16 |
CLkDivisor |
Number of pulses to send out |
RW - - |
0x0064 |
|
3:0 |
DutyCycle |
Duty cycle in percent |
RW - - |
0x7 |
6
|
Description |
: Control of the PWL |
|
Offset |
: 0x2C |
|
Absolute Address |
: 0x57C |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
LUT_SEL |
||||||
|
RW - 0x00 |
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:2 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
1:0 |
LUT_SEL |
Piecewise linear transformation look up table 0x0 DEFAULT0: DEFAULT0 0x1 DEFAULT1: DEFAULT1 0x2 USER0: USER0 0x3 USER1: USER1 |
RW - - |
0x0 |
6
|
Description |
: Instance of exposure to be used in this context |
|
Offset |
: 0x2D |
|
Absolute Address |
: 0x57D |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Instance 0x0 INSTANCE_A: INSTANCE_A 0x1 INSTANCE_B: INSTANCE_B |
RW - - |
0x00 |
6
|
Description |
: Decimation control |
|
Offset |
: 0x2E |
|
Absolute Address |
: 0x57E |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
CFG |
||||||
|
RW - 0x00 |
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:3 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
2:0 |
CFG |
Streaming readout mode control 0x00 NORMAL: = normal streaming 0x01 DBIN_X2: = digital binning x2 0x02 DBIN_X4: = digital binning x4 0x03 SSAMP_X2: = subsampling x2 0x04 SSAMP_X4: = subsampling x4 0x05 SSAMP_X8: = subsampling x8 0x06 XYBINNING_X2: = XY binning x2 |
RW - - |
0x0 |
6
Register: EXPOSURE_MANUAL_COARSE_EXPOSURE_LINES_B
|
Description |
: Manual exposure for the second exposure |
|
Offset |
: 0x30 |
|
Absolute Address |
: 0x580 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0032 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Manual exposure for visible medium |
RW - - |
0x0032 |
6
Register: EXPOSURE_MANUAL_COARSE_EXPOSURE_LINES_C
|
Description |
: Manual exposure for the third exposure |
|
Offset |
: 0x32 |
|
Absolute Address |
: 0x582 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0032 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Manual exposure for visible short |
RW - - |
0x0032 |
6
|
Description |
: Subtraction control |
|
Offset |
: 0x36 |
|
Absolute Address |
: 0x586 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
MODE |
||||||
|
RW - 0x00 |
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:1 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
0 |
MODE |
Mode 0x0 MULTI_EXPO: MULTI_EXPO 0x1 VT_SUB: VT_SUB |
RW - - |
0x0 |
6
|
Description |
: Control to mask frames |
|
Offset |
: 0x37 |
|
Absolute Address |
: 0x587 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
MASK |
||||||
|
RW - 0x00 |
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:1 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
0 |
MASK |
Enable/Disable 0x0 DISABLE: DISABLE 0x1 ENABLE: ENABLE |
RW - - |
0x0 |
6
Block: STREAM_CTX2
|
Description |
: Context2 group elements |
3
|
Description |
: Exposure mode control |
|
Offset |
: 0x0 |
|
Absolute Address |
: 0x5A0 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
MODE |
||||||
|
RW - 0x00 |
RW - 0x2 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:3 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
2:0 |
MODE |
Exposure mode control 0x0 AUTO_MEAN: = automatic mode 0x1 FREEZE: = freeze AE with current settings 0x2 MANUAL: = manual setting mode 0x4 BYPASS: BYPASS |
RW - - |
0x2 |
6
Register: EXPOSURE_MANUAL_ANALOG_GAIN
|
Description |
: Manual analog gain |
|
Offset |
: 0x1 |
|
Absolute Address |
: 0x5A1 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
VALUE |
||||||
|
RW - 0x0 |
RW - 0x00 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:5 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
4:0 |
VALUE |
0x00 AnalogGain_AGAIN_1: AnalogGain_AGAIN_1 0x01 AnalogGain_AGAIN_1_03: AnalogGain_AGAIN_1_03 0x02 AnalogGain_AGAIN_1_07: AnalogGain_AGAIN_1_07 0x03 AnalogGain_AGAIN_1_1: AnalogGain_AGAIN_1_1 0x04 AnalogGain_AGAIN_1_14: AnalogGain_AGAIN_1_14 0x05 AnalogGain_AGAIN_1_19: AnalogGain_AGAIN_1_19 0x06 AnalogGain_AGAIN_1_23: AnalogGain_AGAIN_1_23 0x07 AnalogGain_AGAIN_1_28: AnalogGain_AGAIN_1_28 0x08 AnalogGain_AGAIN_1_33: AnalogGain_AGAIN_1_33 0x09 AnalogGain_AGAIN_1_39: AnalogGain_AGAIN_1_39 0x0A AnalogGain_AGAIN_1_45: AnalogGain_AGAIN_1_45 0x0B AnalogGain_AGAIN_1_52: AnalogGain_AGAIN_1_52 0x0C AnalogGain_AGAIN_1_6: AnalogGain_AGAIN_1_6 0x0D AnalogGain_AGAIN_1_68: AnalogGain_AGAIN_1_68 0x0E AnalogGain_AGAIN_1_78: AnalogGain_AGAIN_1_78 0x0F AnalogGain_AGAIN_1_88: AnalogGain_AGAIN_1_88 0x10 AnalogGain_AGAIN_2: AnalogGain_AGAIN_2 0x11 AnalogGain_AGAIN_2_13: AnalogGain_AGAIN_2_13 0x12 AnalogGain_AGAIN_2_29: AnalogGain_AGAIN_2_29 0x13 AnalogGain_AGAIN_2_46: AnalogGain_AGAIN_2_46 0x14 AnalogGain_AGAIN_2_67: AnalogGain_AGAIN_2_67 0x15 AnalogGain_AGAIN_2_91: AnalogGain_AGAIN_2_91 0x16 AnalogGain_AGAIN_3_2: AnalogGain_AGAIN_3_2 0x17 AnalogGain_AGAIN_3_56: AnalogGain_AGAIN_3_56 0x18 AnalogGain_AGAIN_4: AnalogGain_AGAIN_4 0x19 AnalogGain_AGAIN_4_5714: AnalogGain_AGAIN_4_5714 0x1A AnalogGain_AGAIN_5_3333: AnalogGain_AGAIN_5_3333 0x1B AnalogGain_AGAIN_6_4: AnalogGain_AGAIN_6_4 0x1C AnalogGain_AGAIN_8_0: AnalogGain_AGAIN_8_0 |
RW - - |
0x00 |
6
Register: EXPOSURE_MANUAL_COARSE_EXPOSURE_LINES_A
|
Description |
: Manual coarse exposure |
|
Offset |
: 0x2 |
|
Absolute Address |
: 0x5A2 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0032 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Coarse exposure time in lines |
RW - - |
0x0032 |
6
Register: EXPOSURE_MANUAL_DIGITAL_GAIN_CH0
|
Description |
: Manual digital gain |
|
Offset |
: 0x4 |
|
Absolute Address |
: 0x5A4 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RW - 0x01 |
RW - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Digital gain (integer part) for channel 0 in manual mode |
RW - - |
0x01 |
|
7:0 |
FRACT |
Digital gain (fractional part) for channel 0 in manual mode |
RW - - |
0x00 |
6
|
Description |
: Length of the frame |
|
Offset |
: 0xC |
|
Absolute Address |
: 0x5AC |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0316 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0316 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Length of the frame (including blanking in lines) |
RW - - |
0x0000 0316 |
6
|
Description |
: Y start for image output |
|
Offset |
: 0x10 |
|
Absolute Address |
: 0x5B0 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Y start for image output |
RW - - |
0x0000 |
6
|
Description |
: Y height for image output |
|
Offset |
: 0x12 |
|
Absolute Address |
: 0x5B2 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x02C0 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Y height for image output |
RW - - |
0x02C0 |
6
|
Description |
: X start for image output |
|
Offset |
: 0x14 |
|
Absolute Address |
: 0x5B4 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
X start for image output |
RW - - |
0x0000 |
6
|
Description |
: X wIdth for image output |
|
Offset |
: 0x16 |
|
Absolute Address |
: 0x5B6 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0324 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
X width for image output |
RW - - |
0x0324 |
6
Register: EXPOSURE_STATS_ACTIVE_ZONE
|
Description |
: Active zones for the auto exposure statistique computation |
|
Offset |
: 0x18 |
|
Absolute Address |
: 0x5B8 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0xFFFF |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Active zones for the auto exposure statistique computation |
RW - - |
0xFFFF |
6
Register: EXPOSURE_STATS_ACTIVE_ZONE_WEIGHT
|
Description |
: Statistics zone weight |
|
Offset |
: 0x1A |
|
Absolute Address |
: 0x5BA |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RW - 0x64 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Statistics zone weight |
RW - - |
0x64 |
6
|
Description |
: Marker used by host |
|
Offset |
: 0x1B |
|
Absolute Address |
: 0x5BB |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Marker used by host |
RW - - |
0x00 |
6
|
Description |
: Control of the GPIO 0 |
|
Offset |
: 0x1D |
|
Absolute Address |
: 0x5BD |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
Polarity |
VALUE |
Mode |
||||
|
RW - 0x0 |
RW - 0x0 |
RW - 0x0 |
RW - 0x1 |
||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:6 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
5 |
Polarity |
Polarity value 0x0 NO_INVERSION: NO_INVERSION 0x1 INVERTED: INVERTED |
RW - - |
0x0 |
|
4 |
VALUE |
GPIO value 0x0 GPIO_LOW: GPIO_LOW 0x1 GPIO_HIGH: GPIO_HIGH |
RW - - |
0x0 |
|
3:0 |
Mode |
GPIO mode 0x0 FSYNC_OUT: FSYNC_OUT 0x1 GPIO_IN: GPIO_IN 0x2 STROBE: STROBE 0x3 PWM_STROBE: PWM_STROBE 0x4 PWM: PWM 0x5 GPIO_OUT: GPIO_OUT 0x6 VSYNC_OUT_MODE0: VSYNC_OUT_MODE0 0x7 VSYNC_OUT_MODE1: VSYNC_OUT_MODE1 0x8 VSYNC_OUT_MODE2: VSYNC_OUT_MODE2 0x9 EVENT_TRACKER: EVENT_TRACKER 0xA VT_SLAVE_MODE: VT_SLAVE_MODE 0xC IMAGE_READOUT: IMAGE_READOUT 0xD AWU_DETECTION: AWU_DETECTION |
RW - - |
0x1 |
6
|
Description |
: Control of the GPIO 1 |
|
Offset |
: 0x1E |
|
Absolute Address |
: 0x5BE |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
Polarity |
VALUE |
Mode |
||||
|
RW - 0x0 |
RW - 0x0 |
RW - 0x0 |
RW - 0x2 |
||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:6 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
5 |
Polarity |
Polarity value 0x0 NO_INVERSION: NO_INVERSION 0x1 INVERTED: INVERTED |
RW - - |
0x0 |
|
4 |
VALUE |
GPIO value 0x0 GPIO_LOW: GPIO_LOW 0x1 GPIO_HIGH: GPIO_HIGH |
RW - - |
0x0 |
|
3:0 |
Mode |
GPIO mode 0x0 FSYNC_OUT: FSYNC_OUT 0x1 GPIO_IN: GPIO_IN 0x2 STROBE: STROBE 0x3 PWM_STROBE: PWM_STROBE 0x4 PWM: PWM 0x5 GPIO_OUT: GPIO_OUT 0x6 VSYNC_OUT_MODE0: VSYNC_OUT_MODE0 0x7 VSYNC_OUT_MODE1: VSYNC_OUT_MODE1 0x8 VSYNC_OUT_MODE2: VSYNC_OUT_MODE2 0x9 EVENT_TRACKER: EVENT_TRACKER 0xC IMAGE_READOUT: IMAGE_READOUT 0xD AWU_DETECTION: AWU_DETECTION |
RW - - |
0x2 |
6
|
Description |
: Control of the GPIO 2 |
|
Offset |
: 0x1F |
|
Absolute Address |
: 0x5BF |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
Polarity |
VALUE |
Mode |
||||
|
RW - 0x0 |
RW - 0x0 |
RW - 0x0 |
RW - 0x6 |
||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:6 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
5 |
Polarity |
Polarity value 0x0 NO_INVERSION: NO_INVERSION 0x1 INVERTED: INVERTED |
RW - - |
0x0 |
|
4 |
VALUE |
GPIO value 0x0 GPIO_LOW: GPIO_LOW 0x1 GPIO_HIGH: GPIO_HIGH |
RW - - |
0x0 |
|
3:0 |
Mode |
GPIO mode 0x0 FSYNC_OUT: FSYNC_OUT 0x1 GPIO_IN: GPIO_IN 0x2 STROBE: STROBE 0x3 PWM_STROBE: PWM_STROBE 0x4 PWM: PWM 0x5 GPIO_OUT: GPIO_OUT 0x6 VSYNC_OUT_MODE0: VSYNC_OUT_MODE0 0x7 VSYNC_OUT_MODE1: VSYNC_OUT_MODE1 0x8 VSYNC_OUT_MODE2: VSYNC_OUT_MODE2 0x9 EVENT_TRACKER: EVENT_TRACKER 0xC IMAGE_READOUT: IMAGE_READOUT 0xD AWU_DETECTION: AWU_DETECTION |
RW - - |
0x6 |
6
|
Description |
: Control of the GPIO 3 |
|
Offset |
: 0x20 |
|
Absolute Address |
: 0x5C0 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
Polarity |
VALUE |
Mode |
||||
|
RW - 0x0 |
RW - 0x0 |
RW - 0x0 |
RW - 0x2 |
||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:6 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
5 |
Polarity |
Polarity value 0x0 NO_INVERSION: NO_INVERSION 0x1 INVERTED: INVERTED |
RW - - |
0x0 |
|
4 |
VALUE |
GPIO value 0x0 GPIO_LOW: GPIO_LOW 0x1 GPIO_HIGH: GPIO_HIGH |
RW - - |
0x0 |
|
3:0 |
Mode |
GPIO mode 0x0 FSYNC_OUT: FSYNC_OUT 0x1 GPIO_IN: GPIO_IN 0x2 STROBE: STROBE 0x3 PWM_STROBE: PWM_STROBE 0x4 PWM: PWM 0x5 GPIO_OUT: GPIO_OUT 0x6 VSYNC_OUT_MODE0: VSYNC_OUT_MODE0 0x7 VSYNC_OUT_MODE1: VSYNC_OUT_MODE1 0x8 VSYNC_OUT_MODE2: VSYNC_OUT_MODE2 0x9 EVENT_TRACKER: EVENT_TRACKER 0xC IMAGE_READOUT: IMAGE_READOUT 0xD AWU_DETECTION: AWU_DETECTION |
RW - - |
0x2 |
6
|
Description |
: Capabilty to shift the start of the VSYNC |
|
Offset |
: 0x21 |
|
Absolute Address |
: 0x5C1 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
DELAY_L |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
DELAY_L |
Signed value of the delay to apply in lines |
RW - - |
0x00 |
6
|
Description |
: Capabilty to shift the end of the VSYNC |
|
Offset |
: 0x22 |
|
Absolute Address |
: 0x5C2 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
DELAY_L |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
DELAY_L |
Signed value of the delay to apply in lines |
RW - - |
0x00 |
6
|
Description |
: Capabilty to shift the start of the STROBE |
|
Offset |
: 0x23 |
|
Absolute Address |
: 0x5C3 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
DELAY_L |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
DELAY_L |
Signed value of the delay to apply in lines |
RW - - |
0x00 |
6
|
Description |
: Capabilty to shift the end of the STROBE |
|
Offset |
: 0x24 |
|
Absolute Address |
: 0x5C4 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
DELAY_L |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
DELAY_L |
Signed value of the delay to apply in lines |
RW - - |
0x00 |
6
|
Description |
: Pedestal to be applied |
|
Offset |
: 0x26 |
|
Absolute Address |
: 0x5C6 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0008 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
DarkCal pedestal |
RW - - |
0x0008 |
6
|
Description |
: Controls of the PWM |
|
Offset |
: 0x28 |
|
Absolute Address |
: 0x5C8 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
CLkDivisor |
|||||||||||||||
|
RW - 0x0064 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
DutyCycle |
||||||||||||||
|
|
RW - 0x7 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:16 |
CLkDivisor |
Number of pulses to send out |
RW - - |
0x0064 |
|
3:0 |
DutyCycle |
Duty cycle in percent |
RW - - |
0x7 |
6
|
Description |
: Control of the PWL |
|
Offset |
: 0x2C |
|
Absolute Address |
: 0x5CC |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
LUT_SEL |
||||||
|
RW - 0x00 |
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:2 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
1:0 |
LUT_SEL |
Piecewise linear transformation look up table 0x0 DEFAULT0: DEFAULT0 0x1 DEFAULT1: DEFAULT1 0x2 USER0: USER0 0x3 USER1: USER1 |
RW - - |
0x0 |
6
|
Description |
: Instance of exposure to be used in this context |
|
Offset |
: 0x2D |
|
Absolute Address |
: 0x5CD |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Instance 0x0 INSTANCE_A: INSTANCE_A 0x1 INSTANCE_B: INSTANCE_B |
RW - - |
0x00 |
6
|
Description |
: Decimation control |
|
Offset |
: 0x2E |
|
Absolute Address |
: 0x5CE |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
CFG |
||||||
|
RW - 0x00 |
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:3 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
2:0 |
CFG |
Streaming readout mode control 0x00 NORMAL: = normal streaming 0x01 DBIN_X2: = digital binning x2 0x02 DBIN_X4: = digital binning x4 0x03 SSAMP_X2: = subsampling x2 0x04 SSAMP_X4: = subsampling x4 0x05 SSAMP_X8: = subsampling x8 0x06 XYBINNING_X2: = XY binning x2 |
RW - - |
0x0 |
6
Register: EXPOSURE_MANUAL_COARSE_EXPOSURE_LINES_B
|
Description |
: Manual exposure for the second exposure |
|
Offset |
: 0x30 |
|
Absolute Address |
: 0x5D0 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0032 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Manual exposure for visible medium |
RW - - |
0x0032 |
6
Register: EXPOSURE_MANUAL_COARSE_EXPOSURE_LINES_C
|
Description |
: Manual exposure for the third exposure |
|
Offset |
: 0x32 |
|
Absolute Address |
: 0x5D2 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0032 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Manual exposure for visible short |
RW - - |
0x0032 |
6
|
Description |
: Subtraction control |
|
Offset |
: 0x36 |
|
Absolute Address |
: 0x5D6 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
MODE |
||||||
|
RW - 0x00 |
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:1 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
0 |
MODE |
Mode 0x0 MULTI_EXPO: MULTI_EXPO 0x1 VT_SUB: VT_SUB |
RW - - |
0x0 |
6
|
Description |
: Control to mask frames |
|
Offset |
: 0x37 |
|
Absolute Address |
: 0x5D7 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
MASK |
||||||
|
RW - 0x00 |
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:1 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
0 |
MASK |
Enable/Disable 0x0 DISABLE: DISABLE 0x1 ENABLE: ENABLE |
RW - - |
0x0 |
6
Block: STREAM_CTX3
|
Description |
: Context3 group elements |
3
|
Description |
: Exposure mode control |
|
Offset |
: 0x0 |
|
Absolute Address |
: 0x5F0 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
MODE |
||||||
|
RW - 0x00 |
RW - 0x2 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:3 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
2:0 |
MODE |
Exposure mode control 0x0 AUTO_MEAN: = automatic mode 0x1 FREEZE: = freeze AE with current settings 0x2 MANUAL: = manual setting mode 0x4 BYPASS: BYPASS |
RW - - |
0x2 |
6
Register: EXPOSURE_MANUAL_ANALOG_GAIN
|
Description |
: Manual analog gain |
|
Offset |
: 0x1 |
|
Absolute Address |
: 0x5F1 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
VALUE |
||||||
|
RW - 0x0 |
RW - 0x00 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:5 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
4:0 |
VALUE |
0x00 AnalogGain_AGAIN_1: AnalogGain_AGAIN_1 0x01 AnalogGain_AGAIN_1_03: AnalogGain_AGAIN_1_03 0x02 AnalogGain_AGAIN_1_07: AnalogGain_AGAIN_1_07 0x03 AnalogGain_AGAIN_1_1: AnalogGain_AGAIN_1_1 0x04 AnalogGain_AGAIN_1_14: AnalogGain_AGAIN_1_14 0x05 AnalogGain_AGAIN_1_19: AnalogGain_AGAIN_1_19 0x06 AnalogGain_AGAIN_1_23: AnalogGain_AGAIN_1_23 0x07 AnalogGain_AGAIN_1_28: AnalogGain_AGAIN_1_28 0x08 AnalogGain_AGAIN_1_33: AnalogGain_AGAIN_1_33 0x09 AnalogGain_AGAIN_1_39: AnalogGain_AGAIN_1_39 0x0A AnalogGain_AGAIN_1_45: AnalogGain_AGAIN_1_45 0x0B AnalogGain_AGAIN_1_52: AnalogGain_AGAIN_1_52 0x0C AnalogGain_AGAIN_1_6: AnalogGain_AGAIN_1_6 0x0D AnalogGain_AGAIN_1_68: AnalogGain_AGAIN_1_68 0x0E AnalogGain_AGAIN_1_78: AnalogGain_AGAIN_1_78 0x0F AnalogGain_AGAIN_1_88: AnalogGain_AGAIN_1_88 0x10 AnalogGain_AGAIN_2: AnalogGain_AGAIN_2 0x11 AnalogGain_AGAIN_2_13: AnalogGain_AGAIN_2_13 0x12 AnalogGain_AGAIN_2_29: AnalogGain_AGAIN_2_29 0x13 AnalogGain_AGAIN_2_46: AnalogGain_AGAIN_2_46 0x14 AnalogGain_AGAIN_2_67: AnalogGain_AGAIN_2_67 0x15 AnalogGain_AGAIN_2_91: AnalogGain_AGAIN_2_91 0x16 AnalogGain_AGAIN_3_2: AnalogGain_AGAIN_3_2 0x17 AnalogGain_AGAIN_3_56: AnalogGain_AGAIN_3_56 0x18 AnalogGain_AGAIN_4: AnalogGain_AGAIN_4 0x19 AnalogGain_AGAIN_4_5714: AnalogGain_AGAIN_4_5714 0x1A AnalogGain_AGAIN_5_3333: AnalogGain_AGAIN_5_3333 0x1B AnalogGain_AGAIN_6_4: AnalogGain_AGAIN_6_4 0x1C AnalogGain_AGAIN_8_0: AnalogGain_AGAIN_8_0 |
RW - - |
0x00 |
6
Register: EXPOSURE_MANUAL_COARSE_EXPOSURE_LINES_A
|
Description |
: Manual coarse exposure |
|
Offset |
: 0x2 |
|
Absolute Address |
: 0x5F2 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0032 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Coarse exposure time in lines |
RW - - |
0x0032 |
6
Register: EXPOSURE_MANUAL_DIGITAL_GAIN_CH0
|
Description |
: Manual digital gain |
|
Offset |
: 0x4 |
|
Absolute Address |
: 0x5F4 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
INTEGER |
FRACT |
||||||||||||||
|
RW - 0x01 |
RW - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:8 |
INTEGER |
Digital gain (integer part) for channel 0 in manual mode |
RW - - |
0x01 |
|
7:0 |
FRACT |
Digital gain (fractional part) for channel 0 in manual mode |
RW - - |
0x00 |
6
|
Description |
: Length of the frame |
|
Offset |
: 0xC |
|
Absolute Address |
: 0x5FC |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0316 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0316 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Length of the frame (including blanking in lines) |
RW - - |
0x0000 0316 |
6
|
Description |
: Y start for image output |
|
Offset |
: 0x10 |
|
Absolute Address |
: 0x600 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Y start for image output |
RW - - |
0x0000 |
6
|
Description |
: Y height for image output |
|
Offset |
: 0x12 |
|
Absolute Address |
: 0x602 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x02C0 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Y height for image output |
RW - - |
0x02C0 |
6
|
Description |
: X start for image output |
|
Offset |
: 0x14 |
|
Absolute Address |
: 0x604 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
X start for image output |
RW - - |
0x0000 |
6
|
Description |
: X wIdth for image output |
|
Offset |
: 0x16 |
|
Absolute Address |
: 0x606 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0324 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
X width for image output |
RW - - |
0x0324 |
6
Register: EXPOSURE_STATS_ACTIVE_ZONE
|
Description |
: Active zones for the auto exposure statistique computation |
|
Offset |
: 0x18 |
|
Absolute Address |
: 0x608 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0xFFFF |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Active zones for the auto exposure statistique computation |
RW - - |
0xFFFF |
6
Register: EXPOSURE_STATS_ACTIVE_ZONE_WEIGHT
|
Description |
: Statistics zone weight |
|
Offset |
: 0x1A |
|
Absolute Address |
: 0x60A |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RW - 0x64 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Statistics zone weight |
RW - - |
0x64 |
6
|
Description |
: Marker used by host |
|
Offset |
: 0x1B |
|
Absolute Address |
: 0x60B |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Marker used by host |
RW - - |
0x00 |
6
|
Description |
: Control of the GPIO 0 |
|
Offset |
: 0x1D |
|
Absolute Address |
: 0x60D |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
Polarity |
VALUE |
Mode |
||||
|
RW - 0x0 |
RW - 0x0 |
RW - 0x0 |
RW - 0x1 |
||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:6 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
5 |
Polarity |
Polarity value 0x0 NO_INVERSION: NO_INVERSION 0x1 INVERTED: INVERTED |
RW - - |
0x0 |
|
4 |
VALUE |
GPIO value 0x0 GPIO_LOW: GPIO_LOW 0x1 GPIO_HIGH: GPIO_HIGH |
RW - - |
0x0 |
|
3:0 |
Mode |
GPIO mode 0x0 FSYNC_OUT: FSYNC_OUT 0x1 GPIO_IN: GPIO_IN 0x2 STROBE: STROBE 0x3 PWM_STROBE: PWM_STROBE 0x4 PWM: PWM 0x5 GPIO_OUT: GPIO_OUT 0x6 VSYNC_OUT_MODE0: VSYNC_OUT_MODE0 0x7 VSYNC_OUT_MODE1: VSYNC_OUT_MODE1 0x8 VSYNC_OUT_MODE2: VSYNC_OUT_MODE2 0x9 EVENT_TRACKER: EVENT_TRACKER 0xA VT_SLAVE_MODE: VT_SLAVE_MODE 0xC IMAGE_READOUT: IMAGE_READOUT 0xD AWU_DETECTION: AWU_DETECTION |
RW - - |
0x1 |
6
|
Description |
: Control of the GPIO 1 |
|
Offset |
: 0x1E |
|
Absolute Address |
: 0x60E |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
Polarity |
VALUE |
Mode |
||||
|
RW - 0x0 |
RW - 0x0 |
RW - 0x0 |
RW - 0x2 |
||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:6 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
5 |
Polarity |
Polarity value 0x0 NO_INVERSION: NO_INVERSION 0x1 INVERTED: INVERTED |
RW - - |
0x0 |
|
4 |
VALUE |
GPIO value 0x0 GPIO_LOW: GPIO_LOW 0x1 GPIO_HIGH: GPIO_HIGH |
RW - - |
0x0 |
|
3:0 |
Mode |
GPIO mode 0x0 FSYNC_OUT: FSYNC_OUT 0x1 GPIO_IN: GPIO_IN 0x2 STROBE: STROBE 0x3 PWM_STROBE: PWM_STROBE 0x4 PWM: PWM 0x5 GPIO_OUT: GPIO_OUT 0x6 VSYNC_OUT_MODE0: VSYNC_OUT_MODE0 0x7 VSYNC_OUT_MODE1: VSYNC_OUT_MODE1 0x8 VSYNC_OUT_MODE2: VSYNC_OUT_MODE2 0x9 EVENT_TRACKER: EVENT_TRACKER 0xC IMAGE_READOUT: IMAGE_READOUT 0xD AWU_DETECTION: AWU_DETECTION |
RW - - |
0x2 |
6
|
Description |
: Control of the GPIO 2 |
|
Offset |
: 0x1F |
|
Absolute Address |
: 0x60F |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
Polarity |
VALUE |
Mode |
||||
|
RW - 0x0 |
RW - 0x0 |
RW - 0x0 |
RW - 0x6 |
||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:6 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
5 |
Polarity |
Polarity value 0x0 NO_INVERSION: NO_INVERSION 0x1 INVERTED: INVERTED |
RW - - |
0x0 |
|
4 |
VALUE |
GPIO value 0x0 GPIO_LOW: GPIO_LOW 0x1 GPIO_HIGH: GPIO_HIGH |
RW - - |
0x0 |
|
3:0 |
Mode |
GPIO mode 0x0 FSYNC_OUT: FSYNC_OUT 0x1 GPIO_IN: GPIO_IN 0x2 STROBE: STROBE 0x3 PWM_STROBE: PWM_STROBE 0x4 PWM: PWM 0x5 GPIO_OUT: GPIO_OUT 0x6 VSYNC_OUT_MODE0: VSYNC_OUT_MODE0 0x7 VSYNC_OUT_MODE1: VSYNC_OUT_MODE1 0x8 VSYNC_OUT_MODE2: VSYNC_OUT_MODE2 0x9 EVENT_TRACKER: EVENT_TRACKER 0xC IMAGE_READOUT: IMAGE_READOUT 0xD AWU_DETECTION: AWU_DETECTION |
RW - - |
0x6 |
6
|
Description |
: Control of the GPIO 3 |
|
Offset |
: 0x20 |
|
Absolute Address |
: 0x610 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
Polarity |
VALUE |
Mode |
||||
|
RW - 0x0 |
RW - 0x0 |
RW - 0x0 |
RW - 0x2 |
||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:6 |
RESERVED0 |
Reserved |
RW - - |
0x0 |
|
5 |
Polarity |
Polarity value 0x0 NO_INVERSION: NO_INVERSION 0x1 INVERTED: INVERTED |
RW - - |
0x0 |
|
4 |
VALUE |
GPIO value 0x0 GPIO_LOW: GPIO_LOW 0x1 GPIO_HIGH: GPIO_HIGH |
RW - - |
0x0 |
|
3:0 |
Mode |
GPIO mode 0x0 FSYNC_OUT: FSYNC_OUT 0x1 GPIO_IN: GPIO_IN 0x2 STROBE: STROBE 0x3 PWM_STROBE: PWM_STROBE 0x4 PWM: PWM 0x5 GPIO_OUT: GPIO_OUT 0x6 VSYNC_OUT_MODE0: VSYNC_OUT_MODE0 0x7 VSYNC_OUT_MODE1: VSYNC_OUT_MODE1 0x8 VSYNC_OUT_MODE2: VSYNC_OUT_MODE2 0x9 EVENT_TRACKER: EVENT_TRACKER 0xC IMAGE_READOUT: IMAGE_READOUT 0xD AWU_DETECTION: AWU_DETECTION |
RW - - |
0x2 |
6
|
Description |
: Capabilty to shift the start of the VSYNC |
|
Offset |
: 0x21 |
|
Absolute Address |
: 0x611 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
DELAY_L |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
DELAY_L |
Signed value of the delay to apply in lines |
RW - - |
0x00 |
6
|
Description |
: Capabilty to shift the end of the VSYNC |
|
Offset |
: 0x22 |
|
Absolute Address |
: 0x612 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
DELAY_L |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
DELAY_L |
Signed value of the delay to apply in lines |
RW - - |
0x00 |
6
|
Description |
: Capabilty to shift the start of the STROBE |
|
Offset |
: 0x23 |
|
Absolute Address |
: 0x613 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
DELAY_L |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
DELAY_L |
Signed value of the delay to apply in lines |
RW - - |
0x00 |
6
|
Description |
: Capabilty to shift the end of the STROBE |
|
Offset |
: 0x24 |
|
Absolute Address |
: 0x614 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
DELAY_L |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
DELAY_L |
Signed value of the delay to apply in lines |
RW - - |
0x00 |
6
|
Description |
: Pedestal to be applied |
|
Offset |
: 0x26 |
|
Absolute Address |
: 0x616 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0008 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
DarkCal pedestal |
RW - - |
0x0008 |
6
|
Description |
: Controls of the PWM |
|
Offset |
: 0x28 |
|
Absolute Address |
: 0x618 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
CLkDivisor |
|||||||||||||||
|
RW - 0x0064 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
DutyCycle |
||||||||||||||
|
|
RW - 0x7 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:16 |
CLkDivisor |
Number of pulses to send out |
RW - - |
0x0064 |
|
3:0 |
DutyCycle |
Duty cycle in percent |
RW - - |
0x7 |
6
|
Description |
: Control of the PWL |
|
Offset |
: 0x2C |
|
Absolute Address |
: 0x61C |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
LUT_SEL |
||||||
|
RW - 0x00 |
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:2 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
1:0 |
LUT_SEL |
Piecewise linear transformation look up table 0x0 DEFAULT0: DEFAULT0 0x1 DEFAULT1: DEFAULT1 0x2 USER0: USER0 0x3 USER1: USER1 |
RW - - |
0x0 |
6
|
Description |
: Instance of exposure to be used in this context |
|
Offset |
: 0x2D |
|
Absolute Address |
: 0x61D |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||
|
RW - 0x00 |
|||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:0 |
VALUE |
Instance 0x0 INSTANCE_A: INSTANCE_A 0x1 INSTANCE_B: INSTANCE_B |
RW - - |
0x00 |
6
|
Description |
: Decimation control |
|
Offset |
: 0x2E |
|
Absolute Address |
: 0x61E |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
CFG |
||||||
|
RW - 0x00 |
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:3 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
2:0 |
CFG |
Streaming readout mode control 0x00 NORMAL: = normal streaming 0x01 DBIN_X2: = digital binning x2 0x02 DBIN_X4: = digital binning x4 0x03 SSAMP_X2: = subsampling x2 0x04 SSAMP_X4: = subsampling x4 0x05 SSAMP_X8: = subsampling x8 0x06 XYBINNING_X2: = XY binning x2 |
RW - - |
0x0 |
6
Register: EXPOSURE_MANUAL_COARSE_EXPOSURE_LINES_B
|
Description |
: Manual exposure for the second exposure |
|
Offset |
: 0x30 |
|
Absolute Address |
: 0x620 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0032 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Manual exposure for visible medium |
RW - - |
0x0032 |
6
Register: EXPOSURE_MANUAL_COARSE_EXPOSURE_LINES_C
|
Description |
: Manual exposure for the third exposure |
|
Offset |
: 0x32 |
|
Absolute Address |
: 0x622 |
|
Addressing Mode |
: 32-bits |
4
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0032 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
15:0 |
VALUE |
Manual exposure for visible short |
RW - - |
0x0032 |
6
|
Description |
: Subtraction control |
|
Offset |
: 0x36 |
|
Absolute Address |
: 0x626 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
MODE |
||||||
|
RW - 0x00 |
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:1 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
0 |
MODE |
Mode 0x0 MULTI_EXPO: MULTI_EXPO 0x1 VT_SUB: VT_SUB |
RW - - |
0x0 |
6
|
Description |
: Control to mask frames |
|
Offset |
: 0x37 |
|
Absolute Address |
: 0x627 |
|
Addressing Mode |
: 32-bits |
4
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
RESERVED0 |
MASK |
||||||
|
RW - 0x00 |
RW - 0x0 |
||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
7:1 |
RESERVED0 |
Reserved |
RW - - |
0x00 |
|
0 |
MASK |
Enable/Disable 0x0 DISABLE: DISABLE 0x1 ENABLE: ENABLE |
RW - - |
0x0 |
6
Block: NVM_MIRROR
|
Description |
: V0.1 OTP map |
3
|
Description |
: ENG1 register |
|
Offset |
: 0x8 |
|
Absolute Address |
: 0x648 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
TRND NVM macro test word for pump test |
RW - - |
0x0000 0000 |
6
|
Description |
: ENG2 register |
|
Offset |
: 0xC |
|
Absolute Address |
: 0x64C |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
TRND NVM macro test word for pump test |
RW - - |
0x0000 0000 |
6
|
Description |
: I3C register |
|
Offset |
: 0x5C |
|
Absolute Address |
: 0x69C |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|
||||||||||||||
|
RW - 0x0 |
|
||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
PRODUCT_CODE |
||||||||||||||
|
|
RW - 0x00 |
||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:30 |
VALUE |
|
RW - - |
0x0 |
|
7:0 |
PRODUCT_CODE |
|
RW - - |
0x00 |
6
|
Description |
: I2C_ADDRESS register |
|
Offset |
: 0x78 |
|
Absolute Address |
: 0x6B8 |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
I2C_KEY |
|
I2C_DEVICEID_3 |
|||||||||||||
|
RW - 0x00 |
|
RW - 0x00 |
|||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
I2C_DEVICEID_2 |
|
I2C_DEVICEID_1 |
||||||||||||
|
|
RW - 0x00 |
|
RW - 0x00 |
||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:24 |
I2C_KEY |
if I2C key = 0xAA, update I2C address |
RW - - |
0x00 |
|
22:16 |
I2C_DEVICEID_3 |
Device I2C address |
RW - - |
0x00 |
|
14:8 |
I2C_DEVICEID_2 |
Device I2C address |
RW - - |
0x00 |
|
6:0 |
I2C_DEVICEID_1 |
Device I2C address |
RW - - |
0x00 |
6
|
Description |
: CTM_AREA_n register |
|
Offset |
: [0x7C - 0xF8] |
|
Absolute Address |
: [0x6BC - 0x738] |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
VALUE |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
VALUE |
Customer area |
RW - - |
0x0000 0000 |
6
|
Description |
: LAST_WORD register |
|
Offset |
: 0xFC |
|
Absolute Address |
: 0x73C |
|
Addressing Mode |
: 32-bits |
4
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
LAST_WORD |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
LAST_WORD |
|||||||||||||||
|
RW - 0x0000 0000 |
|||||||||||||||
5
|
Bit |
Name |
Description |
SW Access HW Access Protection |
Reset |
|
31:0 |
LAST_WORD |
|
RW - - |
0x0000 0000 |
6
Access policy
|
Access policy |
Description |
Effect of a Write on Current Field Value |
Effect of a Read on Current Field Value |
|
RO |
Read Only |
No effect. |
No effect. |
|
RW |
Read Write |
Changed to written value. |
No effect. |
7